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FDMF8700 Driver plus FET Multi-chip Module
March 2007
FDMF8700
Driver plus FET Multi-chip Module
Benefits
Fully optimized system efficiency. Higher efficiency levels
are achievable compared with conventional discrete
components.
Space savings of up to 50% PCB versus discrete solutions.
Higher frequency of operation.
Simpler system design and board layout. Reduced time in
component selection and optimization.
tm
General Description
The FDMF8700 is a fully optimized integrated 12V Driver plus
MOSFET power stage solution for high current synchronous
buck DC-DC applications. The device integrates a driver IC and
two Power MOSFETs into a space saving, 8mm x 8mm, 56-pin
Power88™ package. Fairchild Semiconductor’s integrated
approach optimizes the complete switching power stage with
regards to driver to FET dynamic performance, system
inductance and overall solution ON resistance. Package
parasitics and problematical layouts associated with
conventional discrete solutions are greatly reduced. This
integrated approach results in significant board space saving,
therefore maximizing footprint power density. This solution is
based on the Intel™ DrMOS specification.
Features
12V typical Input Voltage
Output current up to 30A
500KHz switching frequency capable
Internal adaptive gate drive
Integrated bootstrap diode
Peak Efficiency >90%
Under-voltage Lockout
Output disable for lost phase shutdown
Low profile SMD package
RoHS Compliant
Applications
Desktop and server VR11.x V-core and non V-core buck
converters.
CPU/GPU power train in game consoles and high end
desktop systems.
High-current DC-DC Point of Load (POL) converters
Networking and telecom microprocessor voltage regulators
Small form factor voltage regulator modules
Powertrain Application Circuit
12V
C
VCC
VCIN
DISB
PWM
Input
DISB
VIN
BOOT
C
BOOT
PWM
CGND
VSWH
PGND
C
OUT
OUTPUT
Figure 1. Powertrain Application Circuit
Ordering Information
Current Rating
Max
[A]
30
Input Voltage
Typical
[V]
12
1
Frequency
Max
[KHz]
500
Device
Marking
FDMF8700
www.fairchildsemi.com
Part
FDMF8700
©2007 Fairchild Semiconductor Corporation
FDMF8700 Rev. C3
FDMF8700 Driver plus FET Multi- chip Module
Functional Block Diagram
BOOT VCIN
HDRV
VIN
DISB
PWM
2.2
1.2
VSWH
1.2
VCIN
CGND
LDRV
PGND
Figure 2. Functional Block Diagram
Pin Configuration
CGND
NC
NC
VCIN
BOOT
CGND
VSWH
VIN
VIN
TEST PAD1
VIN
VIN
VIN
VIN
1
PWM 56
DISB
NC
NC
NC
CGND
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH 43
14
15 VIN
VIN
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
28 PGND
29
(CGND)
(VIN)
(VSWH)
42
Figure 3. Power88 56L Bottom View
VSWH
VSWH
VSWH
TEST PAD2
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
2
FDMF8700 Rev. C3
www.fairchildsemi.com
FDMF8700 Driver plus FET Multi- chip Module
Pin Description
Pin
1,6,51
2,3,52,53,54
4
5
7,21,40-50
8,9,11-20
10
22-38
39
55
56
Name
CGND
NC
VCIN
BOOT
VSWH
VIN
TEST PAD 1
PGND
TEST PAD 2
DISB
PWM
IC Ground. Ground return for driver IC.
No connect
Function
IC Supply. +12V chip bias power. Bypass with a 1µF ceramic capacitor.
Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver. Connect
bootstrap capacitor.
Switch Node Input. SW Provides return for high-side bootstrapped driver and acts as a
sense point for the adaptive shoot-thru protection.
Power Input. Output stage supply voltage.
For manufacturing test only. HDRV pin. This pin must be floated. Must not be connected to
any pin.
Power ground. Output stage ground. Source pin of low side MOSFET(s).
For manufacturing test only. LDRV pin. This pin must be floated. Must not be connected to
any pin.
Output Disable. When low, this pin disable FET switching (HDRV and LDRV are held low).
PWM Signal Input. This pin accepts a logic-level PWM signal from the controller.
Absolute Maximum Rating
Parameter
V
CIN
to PGND
V
IN
to PGND
PWM, DSIB to GND
VSWH to PGND
BOOT to VSWH
BOOT to PGND
I
O(AV)
I
O(PK)
R
θJPCB
P
D
Continuous
Transient (t = 100ns, f
sw
= 500KHz)
V
IN
= 12V, V
O
= 1.3V, f
sw
= 500KHz, T
PCB
= 100°C
V
IN
= 12V, t
PULSE
= 10µs
Junction to PCB Thermal Resistance (note 1)
T
PCB
= 100°C (note 1)
-55
Continuous
Transient (t = 100ns, f
sw
= 500KHz)
Min.
-0.5
-0.5
-0.3
-1
-5
-0.3
-0.3
-0.3
Max.
15
15
5.5
15
25
15
30
33
30
65
5.5
9.1
150
Units
V
V
V
V
V
V
V
V
A
A
°C/W
W
°C
Operating and Storage Junction Temperature Range
Recommended Operating Range
Parameter
V
CIN
V
IN
Control Circuit Supply Voltage
Output Stage Supply Voltage
Min.
6.4
6.4
Typ.
12
12
Max.
13.5
14
Units
V
V
Electrical Characteristics
V
IN
= 12V, T
A
= 25°C unless otherwise noted.
Parameter
Control Circuit Supply Current
Undervoltage lockout threshold
PWM Input High Voltage
Symbol
I
CIN
V
TH(UVLO)(2)
V
IH(PWM)
Conditions
f
SW
= 0Hz, V
DISB
= 0V
f
SW
= 500KHz, V
DISB
= 5V
Turn-on
Turn-off
Min.
Typ.
3.5
18
6
5.25
Max.
8
Units
mA
V
V
V
3.5
FDMF8700 Rev. C3
3
www.fairchildsemi.com
FDMF8700 Driver plus FET Multi- chip Module
Electrical Characteristics
V
IN
= 12V, T
A
= 25°C unless otherwise noted
.
Parameter
PWM Input Low Voltage
PWM Input Current
Output Disable Input High Voltage
Output Disable Input Low Voltage
Output Disable Input Current
Output Stage Leakage Current
Symbol
V
IL(PWM)
I
PWM
V
IH(DISB)
V
IL(DISB)
I
DISB
I
IN_LEAKAGE
t
PDL(LDRV)(3)
Conditions
Min.
-1
2.5
Typ.
Max.
0.8
1
0.8
Units
V
µA
V
V
µA
µA
ns
ns
ns
ns
-1
V
DISB
= 0V
250
48
37
34
51
f
sw
= 500KHz, I
O
= 30A
1
Propagation Delay
t
PDL(HDRV)(3)
V
IN
= 12V, V
OUT
= 1.3V,
t
PDH(LDRV)(3)
t
PDH(HDRV)(3)
Note 1:
Package power dissipation based on 4 layer, 2 square inch, 2 oz. copper pad. R
θJPCB
is the steady state junction to PCB
thermal resistance with PCB temperature referenced at VSWH pin.
Note 2:
When combined with controller, driver UVLO must be less than that of controller.
Note 3:
t
PDL(LDRV/HRDV)
refers to HIGH-to-LOW transition, t
PDH(LDRV/HDRV)
refers to LOW-to-HIGH transition.
FDMF8700 Rev. C3
4
www.fairchildsemi.com
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