82567
GbE Physical Layer Transceiver (PHY)
Datasheet
Product Features
Reduced power consumption during normal
operation and power down modes
IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE-TX, and 10BASE-T applications
(802.3, 802.3u, and 802.3ab) conformance
Supports up to 9 kB jumbo frames (full
duplex)
Supports carrier extension (half duplex)
Auto-negotiation with support for next page
Smart speed operation, for automatic speed
reduction on faulty cable plants
Automatic MDI crossover capable
PMA loopback capable (No echo cancel)
Advanced power management:
— Low power link up
— Auto Connect Battery Saver - link
disconnect
Advanced cable diagnostics:
— TDR
— Channel frequency response
Extended configuration load sequence
Automatic resolution of FDX/HDX mismatch in
10/100 forced configurations
Dual interconnect between MAC and PHY:
— LCI for 10/100 Mb/s operation control traffic
— GLCI for 1000 Mb/s operation
Three LED outputs
Multiple voltage regulation modes:
— External voltage regulation
— Fully integrated linear regulator (nominal
1.05 V, programmable)
— Discrete linear voltage regulator (nominal
1.8 V-1.9 V)
Supported ICH Integrated MAC Features:
— Linksec (ICH10 only)
— Manageability: vPro Compatible
— Performance:
•RSS Support
•Checksum offload
Order Number: 321792-001
Revision
2.4
April 2009
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use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
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for details.
This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not
finalize a design with this information.
The 82567 GbE Physical Layer Transceiver may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Hyper-Threading Technology requires a computer system with an Intel
®
Pentium
®
4 processor supporting HT Technology and a HT Technology enabled
chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See
http://www.intel.com/
products/ht/Hyperthreading_more.htm
for additional information.
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*Other names and brands may be claimed as the property of others.
Copyright © 2006-2009, Intel Corporation. All Rights Reserved.
ii
Datasheet—82567
Contents
1.0
Introduction
.............................................................................................................. 5
1.1
Scope ................................................................................................................ 6
1.2
Reference Documents .......................................................................................... 6
1.3
Product Codes..................................................................................................... 6
Signal Descriptions
.................................................................................................... 7
2.1
Signal Type Definitions......................................................................................... 7
2.2
GLCI Interface Pins.............................................................................................. 7
2.3
LCI Interface Pins................................................................................................ 8
2.4
Miscellaneous Pins ............................................................................................... 8
2.5
PHY Pins ............................................................................................................ 9
2.5.1 LED Pins ................................................................................................. 9
2.5.2 Analog Pins ............................................................................................. 9
2.5.3 Testability Pins......................................................................................... 9
2.6
Power Supply Pins ............................................................................................. 10
Features
.................................................................................................................. 11
3.1
Feature Matrix and Product Information................................................................ 11
3.2
Power Saving Features....................................................................................... 12
3.2.1 Intel
®
Auto Connect Battery Saver (ACBS) ................................................ 12
3.2.2 Link Speed Battery Saver ........................................................................ 12
3.2.3 System Idle Power Saver (SIPS) .............................................................. 13
3.2.4 Low Power Link Up (LPLU) ....................................................................... 13
3.2.5 LAN Disable ........................................................................................... 14
Voltage, Temperature, and Timing Specifications
.................................................... 16
4.1
Recommended Operating Conditions .................................................................... 16
4.2
DC and AC Characteristics .................................................................................. 16
4.3
LED Electrical Specification ................................................................................. 16
4.4
Crystal Specifications ......................................................................................... 17
4.5
Oscillator Specifications...................................................................................... 19
4.5.1 Oscillator High Voltage Configuration ........................................................ 19
4.6
Power Consumption ........................................................................................... 20
4.7
Power Delivery.................................................................................................. 23
4.7.1 The 1.8 V-1.9 V Rail ............................................................................... 23
4.7.2 The 1.05 V Rail ...................................................................................... 23
4.7.3 Voltage Regulator Schematics .................................................................. 23
4.7.4 Voltage Regulator Power Supply Specifications ........................................... 24
4.7.5 PNP Specifications .................................................................................. 25
4.7.6 Power Sequencing .................................................................................. 25
4.8
Timing Parameters ............................................................................................ 26
4.8.1 Timing Requirements .............................................................................. 26
4.8.2 Timing Guarantees ................................................................................. 26
Package and Pinout Information
............................................................................. 27
5.1
Package Information.......................................................................................... 27
5.2
Thermal ........................................................................................................... 27
5.3
Internal Pull-Up Resistors ................................................................................... 28
5.4
Visual Pin Assignments....................................................................................... 29
2.0
3.0
4.0
5.0
iii
82567—Datasheet
Revision History
Date
Oct 2006
January 2007
February 2007
April 2007
May 2007
August 2007
September
2007
November 2007
November 2007
December 2007
Revision
0.1
0.25
0.26
0.50
0.51
0.75
Description
Initial release (Intel secret)
Corrected pin numbers and made minor text corrections (Intel Confidential)
Corrected GLAN TX pin numbers; added RSET & DIS_REG1_0 to the signal descriptions; corrected
LAN_DISABLE# (active high) to LAN_DISABLE_N (active low); in the Visual Pin Assignment
Diagram, pin 37, “LAN Enable” was corrected to “LAN_Disable_N”; removed VHV references.
Minor text updates.
Updated power consumption target values.
Added Low-Power feature information, Recommended Operating Conditions, DC and AC
Characteristics, Preliminary LED/TEST/JTAG I/F DC Specifications, Crystal Specification, Voltage
RegulatorPower Supply Specification, PnP Transistor Specification, and Power Sequencing
information.
Changed IEEE 802.3ab designation to conformance
Updated features list; updated Reference Documents; added SKU information; Updated power rail
information (1.8 V-1.9 V, 1.05 V); clarified oscillator placement information; updated power target
information; corrected Slope and Operation Range characteristics for 1.8-1.9 V rail; added pointer
to reference schematics for regulator information.
Deleted “programmable” from 1.8 V-1.9 V power rail listing in the Features list.
Corrected 1.05 V power rail tolerance to +7% / -5% (1.0 V min, 1.12 V max)
Added XOR test file information; updated SKU and Features table; added information regarding
using LAN_PHY_PWR_CTRL ; updated Recommended Operating Conditions; updated DC and AC
characteristics; updated crystal/oscillator specifications; updated the measured power
consumption values; updated reference schematic link information; updated the 1.8 V-1.9 V rail
operational range value; updated the 1.05 V rail operational range value; corrected P
tot
Min value
in PNP specification;
Updated Reference Documents list; updated Testability Pins table; updated SKU table; updated
Power Consumption tables 7-10; updated power delivery drawing; added Ambient Operating
Temperature table.
Updated SKU table; Combined Tables 5 and 6 to create new Table 5.
Updated Table 2.4 (added pull-up type designation to LAN_DISABLE_N); updated Table 12 (added
LAN_DISABLE_N information)
Updated WoL information; added System Idle Power Saver information; updated crystal
tolerances; updated LED pin table; updated pinout illustration; updated package tolerance values.
Updated SKU table; added SPI
FLASH Programming Guide
and
82567 Specification Update
to
Reference Documents; added note regarding ACBS operation; added WoL power information;
added Solution Power information to Power Consumption table; clarified crystal Drive Level
specification.
0.76
1.5
1.51
1.6
February 2008
1.7
March 2008
March 2008
April 2008
July 2008
2.0
2.1
2.2
2.3
April 2009
2.4
Note:
The revision numbering system changed with the first November 2007 release. At that time, the collateral for this device
began synchronizing with platform collateral revision numbering. There were no releases between versions 0.76 and 1.5.
iv
Datasheet—82567
1.0
Introduction
The 82567 is a single port GbE Physical Layer Transceiver (PHY) that connects to its
Media Access Controller (MAC) through a dedicated interconnect. The 82567 is based
on Intel's GbE PHY technology, and supports operation at data rates of 10/100/1000
Mb/s. The physical layer circuitry provides a standard IEEE 802.3 Ethernet interface for
10BASE-T, 100BASE-TX, and 1000BASE-T applications (802.3, 802.3u, and 802.3ab).
The 82567 operates with the ICH9/9M/10 chipset that incorporates and integrates the
MAC, which is referred to as the ICH9/9M/10 LAN.
The 82567 is packaged in a small footprint QFN package. The package size is 8 mm x 8
mm with a pin-to-pin spacing of 0.5 mm, making it attractive for small form-factor
platforms.
The 82567 interfaces with its MAC through two interfaces: Gigabit LAN Connect
Interface (GLCI) and LAN Connect Interface (LCI). The GLCI is a high-speed proprietary
serial interface. The LCI is a low-speed proprietary parallel bus. The 82567 operates
using both interfaces; the GLCI for 1000 Mb/s traffic and LCI for all other traffic types.
Figure 1
identifies the major components of the 82567 architecture.
LCI
GLCI
LCI
GLCI
Crystal
PLL
Multiplexer
LEDs
Testability
MDIO
Status & Control
Power
Power
Supply
PHY
82567
MDI
Figure 1.
82567 Block Diagram
5
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