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82583V: DescriptionIntelÂ® 82583V GbE Controller; File Size5MB，374 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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82583V Overview

IntelÂ® 82583V GbE Controller

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Intel® 82583V GbE Controller

Datasheet

Product Features



PCI Express* (PCIe*)

— 64-bit address master support for systems

using more than 4 GB of physical memory

— Programmable host memory receive buffers

(256 bytes to 16 KB)

— Intelligent interrupt generation features to

enhance driver performance

— Descriptor ring management hardware for

transmit and receive software controlled reset

(resets everything except the configuration

space)

— Message Signaled Interrupts (MSI)

— Configurable receive and transmit data FIFO,

programmable in 1 KB increments



High Performance

— TCP segmentation capability compatible with

Large Send offloading features

— Support up to 256 KB TCP segmentation (TSO

v2)

— Fragmented UDP checksum offload for packet

reassemble

— IPv4 and IPv6 checksum offload support

(receive, transmit, and large send)

— Split header support

— 40 KB packet buffer size



Low Power



MAC

— Flow Control Support compliant with the

802.3X Specification

— VLAN support compliant with the 802.1Q

Specification

— MAC Address filters: perfect match unicast

— filters; multicast hash filtering, broadcast filter

— and promiscuous mode

— Statistics for RMOM

— MAC loopback

— Magic Packet* wake-up enable with unique

MAC address

— ACPI register set and power down functionality

supporting D0 andD3 states

— Full wake up support (APM and ACPI 2.0)

— Smart power down at S0 no link and Sx no link

— LAN disable function



Technology



PHY

— 9 mm x 9 mm 64-pin QFN package with

Exposed Pad*

— Configurable LED operation for customization

of LED displays

— Compliant with the 1 Gb/s IEEE 802.3 802.3u

802.3ab Specifications

— IEEE 802.3ab auto negotiation support

— Full duplex operation at 10/100/1000 Mb/s

— Half duplex at 10/100 Mb/s

— Auto MDI, MDI-X crossover at all speeds

June 2012

Revision 2.5

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics

of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever

for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design

with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-

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Datasheet—82583V GbE Controller

Contents

1.0

Introduction

............................................................................................................ 10

1.1

Scope .............................................................................................................. 10

1.2

Number Conventions ......................................................................................... 10

1.3

Acronyms......................................................................................................... 11

1.4

Reference Documents ........................................................................................ 11

1.5

82583V Architecture Block Diagram ..................................................................... 12

1.6

System Interface............................................................................................... 12

1.7

Features Summary ............................................................................................ 12

1.8

Product Codes................................................................................................... 15

Pin Interface

........................................................................................................... 16

2.1

Pin Assignments................................................................................................ 16

2.2

Pull-Up/Pull-Down Resistors and Strapping Options ................................................ 17

2.3

Signal Type Definition ........................................................................................ 17

2.3.1 PCIe ..................................................................................................... 17

2.3.2 NVM Port............................................................................................... 18

2.3.3 LEDs .................................................................................................... 18

2.3.4 PHY Pins ............................................................................................... 19

2.3.5 Miscellaneous and Test Pins ..................................................................... 20

2.3.6 Power Supplies and Support Pins .............................................................. 21

2.3.7 Reserved Pins ........................................................................................ 21

2.4

Package ........................................................................................................... 22

Electrical Specifications

........................................................................................... 24

3.1

Introduction ..................................................................................................... 24

3.2

Voltage Regulator Power Supply Specification ....................................................... 24

3.2.1 3.3 V dc Rail .......................................................................................... 24

3.2.2

1.9 V dc Rail ......................................................................................... 24

3.2.3 1.05 V dc Rail ........................................................................................ 25

3.2.4

PNP Specifications ................................................................................. 25

3.3

Power Sequencing ............................................................................................. 26

3.4

Power-On Reset ................................................................................................ 26

3.5

Power Scheme Solutions .................................................................................... 27

3.6

Flash AC Specifications....................................................................................... 30

3.7

EEPROM AC Specifications .................................................................................. 31

3.8

Discrete/Integrated Magnetics Specifications......................................................... 32

3.9

Oscillator/Crystal Specifications........................................................................... 33

3.10 I/O DC Parameters ............................................................................................ 34

3.10.1 LEDs .................................................................................................... 35

Initialization............................................................................................................

4.1

Introduction ..................................................................................................... 36

4.2

Reset Operation ................................................................................................ 36

4.3

Power Up ......................................................................................................... 38

4.3.1 Power-Up Sequence................................................................................ 38

4.3.2 Timing Diagram ..................................................................................... 46

4.4

Global Reset (PE_RST_N, PCIe In-Band Reset) ...................................................... 47

4.4.1 Reset Sequence ..................................................................................... 47

4.4.2 Timing Diagram ..................................................................................... 48

4.5

Timing Parameters ............................................................................................ 50

4.5.1 Timing Requirements .............................................................................. 50

4.5.2 MDIO and NVM Semaphore...................................................................... 50

2.0

3.0

4.0

82583V GbE Controller—Datasheet

4.6

Software Initialization Sequence ..........................................................................51

4.6.1 Interrupts During Initialization..................................................................51

4.6.2 Global Reset and General Configuration .....................................................51

4.6.3 Link Setup Mechanisms and Control/Status Bit Summary .............................52

4.6.4 Initialization of Statistics..........................................................................53

4.6.5 Receive Initialization ...............................................................................54

4.6.6 Transmit Initialization..............................................................................54

5.0

Non-Volatile Memory (NVM) Map

.............................................................................56

5.1

Basic Configuration Table....................................................................................56

5.1.1 Hardware Accessed Words .......................................................................58

5.1.2 Software Accessed Words ........................................................................72

Interconnects

..........................................................................................................80

6.1

PCIe ................................................................................................................80

6.1.1 Architecture, Transaction, and Link Layer Properties ....................................81

6.1.2 General Functionality ..............................................................................82

6.1.3 Transaction Layer ...................................................................................82

6.1.4 Flow Control...........................................................................................87

6.1.5 Host I/F.................................................................................................89

6.1.6 Error Events and Error Reporting ..............................................................90

6.1.7 Link Layer..............................................................................................93

6.1.8 PHY ......................................................................................................94

6.1.9 Performance Monitoring ...........................................................................95

6.2

Ethernet Interface .............................................................................................95

6.2.1 MAC/PHY GMII/MII Interface ....................................................................95

6.2.2 Duplex Operation for Copper PHY/GMII/MII Operation .................................96

6.2.3 Auto-Negotiation & Link Setup Features .....................................................97

6.2.4 Loss of Signal/Link Status Indication ....................................................... 100

6.2.5 10/100 Mb/s Specific Performance Enhancements ..................................... 101

6.2.6 Flow Control......................................................................................... 102

6.3

SPI Non-Volatile Memory Interface..................................................................... 105

6.3.1 General Overview ................................................................................. 105

6.3.2 Supported NVM Devices......................................................................... 105

6.3.3 NVM Device Detection ........................................................................... 106

6.3.4 Device Operation with an External EEPROM .............................................. 107

6.3.5 Device Operation with Flash ................................................................... 107

6.3.6 Shadow RAM ........................................................................................ 107

6.3.7 NVM Clients and Interfaces .................................................................... 109

6.3.8 NVM Write and Erase Sequence .............................................................. 110

Inline Functions

..................................................................................................... 114

7.1

Packet Reception ............................................................................................. 114

7.1.1 Packet Address Filtering......................................................................... 114

7.1.2 Receive Data Storage ............................................................................ 115

7.1.3 Legacy Receive Descriptor Format........................................................... 115

7.1.4 Extended Rx Descriptor ......................................................................... 118

7.1.5 Packet Split Receive Descriptor............................................................... 123

7.1.6 Receive Descriptor Fetching ................................................................... 127

7.1.7 Receive Descriptor Write Back ................................................................ 127

7.1.8 Receive Descriptor Queue Structure ........................................................ 128

7.1.9 Receive Interrupts ................................................................................ 130

7.1.10 Receive Packet Checksum Offloading ....................................................... 133

6.0

7.0

Datasheet—82583V GbE Controller

7.2

7.3

7.4

7.5

7.6

8.0

Packet Transmission ........................................................................................ 135

7.2.1 Transmit Functionality........................................................................... 135

7.2.2 Transmission Flow Using Simplified Legacy Descriptors.............................. 136

7.2.3 Transmission Process Flow Using Extended Descriptors.............................. 136

7.2.4 Transmit Descriptor Ring Structure ......................................................... 137

7.2.5 Overview of On-Chip Transmit Modes...................................................... 139

7.2.6 Pipelined Tx Data Read Requests ............................................................ 140

7.2.7 Transmit Interrupts .............................................................................. 141

7.2.8 Transmit Data Storage .......................................................................... 141

7.2.9 Transmit Descriptor Formats.................................................................. 142

7.2.10 Extended Data Descriptor Format ........................................................... 150

TCP Segmentation ........................................................................................... 154

7.3.1 TCP Segmentation Performance Advantages ............................................ 154

7.3.2 Ethernet Packet Format......................................................................... 154

7.3.3 TCP Segmentation Data Descriptors........................................................ 155

7.3.4 TCP Segmentation Source Data .............................................................. 156

7.3.5 Hardware Performed Updating for Each Frame ......................................... 156

7.3.6 TCP Segmentation Use of Multiple Data Descriptors .................................. 157

Interrupts ...................................................................................................... 160

7.4.1 Legacy and MSI Interrupt Modes ............................................................ 160

7.4.2 Registers............................................................................................. 160

7.4.3 Interrupt Moderation ............................................................................ 161

7.4.4 Clearing Interrupt Causes...................................................................... 164

802.1q VLAN Support ...................................................................................... 165

7.5.1 802.1q VLAN Packet Format .................................................................. 165

7.5.2 Transmitting and Receiving 802.1q Packets ............................................. 166

7.5.3 802.1q VLAN Packet Filtering ................................................................. 166

LEDs.............................................................................................................. 167

Power Management and Delivery...........................................................................

170

8.1

Assumptions................................................................................................... 170

8.2

Power Consumption ......................................................................................... 170

8.3

Power Delivery................................................................................................ 171

8.3.1 The 1.9 V dc Rail .................................................................................. 171

8.3.2 The 1.05 V dc Rail ................................................................................ 171

8.4

Power Management ......................................................................................... 171

8.4.1 82583V Power States............................................................................ 171

8.4.2 Auxiliary Power Usage........................................................................... 172

8.4.3 Power Limits by Certain Form Factors ..................................................... 173

8.4.4 Power States ....................................................................................... 173

8.4.5 Timing of Power-State Transitions .......................................................... 177

8.5

Wake Up ........................................................................................................ 180

8.5.1 Advanced Power Management Wake Up .................................................. 180

8.5.2 PCIe Power Management Wake Up.......................................................... 181

8.5.3 Wake-Up Packets ................................................................................. 181

Driver Programing Interface..................................................................................

188

9.1

Introduction ................................................................................................... 188

9.1.1 Memory and I/O Address Decoding ......................................................... 188

9.1.2 Registers Byte Ordering ........................................................................ 191

9.1.3 Register Conventions ............................................................................ 191

9.0

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