P re li m i n a r y D at a S h e e t , D S 1 , J u l y 2 00 2
TSLIC-E
Twin Subscriber Line Interface
Circuit Enhanced Feature Set
PEB 4365 Version 1.1
Wi re d
Communications
N e v e r
s t o p
t h i n k i n g .
TSLIC-E
Preliminary
Revision History:
Previous Version:
Page
2002-07-17
none
DS1
Subjects (major changes since last revision)
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
Edition 2002-07-17
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2002.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
PEB 4365
Table of Contents
1
1.1
1.2
1.3
1.4
1.5
2
2.1
2.2
3
4
4.1
4.2
4.3
4.4
4.5
4.6
4.6.1
4.6.2
4.6.3
5
6
6.1
Page
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Current Limitation / Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Typical Application Circuit for DuSLIC and VINETIC
. . . . . . . . . . . . . . 18
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Foreign Line Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Up Sequence of Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Currents and Power Dissipation (Values per Channel) . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
22
23
23
24
24
27
30
Test Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Recommended PCB Foot Print Pattern for the P-DSO-36-10 . . . . . . . . . . 39
Preliminary Data Sheet
3
DS1, 2002-07-17
PEB 4365
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Page
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram (one Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Definition of Output Current Directions . . . . . . . . . . . . . . . . . . . . . . . . 15
Application Circuit DuSLIC (only Channel A connected) . . . . . . . . . . . 19
Application Circuit VINETIC (only Channel A connected) . . . . . . . . . . 20
Typical Buffer Voltage Drop in Operating Modes ACTL, ACTH, ACTR 29
Typical Frequency Dependance of PSRR VBATL/VTR. . . . . . . . . . . . 32
Typical Frequency Dependance of PSRR VBATH/VTR . . . . . . . . . . . 33
Typical Frequency Dependance of PSRR VDD/VTR . . . . . . . . . . . . . 33
Output Current Limit (one Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Output Resistance PDRH, PDRHL (one Channel) . . . . . . . . . . . . . . . 34
Current Outputs IT, IL (one Channel) . . . . . . . . . . . . . . . . . . . . . . . . . 35
Transmission Characteristics (one Channel) . . . . . . . . . . . . . . . . . . . . 35
Longitudinal to Transversal Rejection (one Channel) . . . . . . . . . . . . . 36
Longitudinal to Transversal Rejection Loop (one Channel) . . . . . . . . . 36
Transversal to Longitudinal Rejection (one Channel) . . . . . . . . . . . . . 37
Ring Amplitude (one Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Package Outline P-DSO-36-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Foot Print for P-DSO-36-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Preliminary Data Sheet
4
DS1, 2002-07-17
PEB 4365
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Page
11
16
16
18
21
22
22
23
23
24
26
26
27
30
Pin Definitions and Functions TSLIC-E . . . . . . . . . . . . . . . . . . . . . . . .
TSLIC-E Interface Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSLIC-E Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Components DuSLIC / VINETIC for 2 Channels . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Limits on Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Limits on Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Currents, Power Dissipation (
I
R
=
I
T
= 0 A;
V
RT
= 0 V) . . . . . .
Voltage Dependence of Supply Currents. . . . . . . . . . . . . . . . . . . . . . .
Output Stage Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Data Sheet
5
DS1, 2002-07-17
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