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85304AG-01LFT

Description
Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer
File Size388KB,15 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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85304AG-01LFT Overview

Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer

Low Skew, 1-to-5, Differential-to-3.3V
LVPECL Fanout Buffer
Data Sheet
85304-01
General Description
The 85304-01 is a low skew, high performance 1-to-5
Differential-to-3.3V LVPECL fanout buffer. The 85304-01 has two
selectable clock inputs. The CLKx, nCLKx pairs can accept most
standard differential input levels. The clock enable is internally
synchronized to eliminate runt clock pulses on the outputs during
asynchronous assertion/ deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
85304-01 ideal for those applications demanding well defined
performance and repeatability.
Features
Five 3.3V differential LVPECL output pairs
Selectable differential CLKx, nCLKx input pairs
CLKx, nCLKx input pairs can accept the following differential
levels: LVDS, LVPECL, LVHSTL, SSTL and HCSL levels
Maximum output frequency: 650MHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nCLKx inputs
Output skew: 35ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 2.1ns (maximum)
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Block Diagram
CLK_EN
Pullup
D
Q
CLK0
Pulldown
nCLK0
Pullup
CLK1
Pulldown
nCLK1
Pullup
CLK_SEL
Pulldown
LE
0
0
1
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
CLK_EN
V
CC
nCLK1
CLK1
V
EE
nCLK0
CLK0
CLK_SEL
V
CC
85304-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
© 2015 Integrated Device Technology, Inc
1
Revision E
December 2, 2015
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