Register Map: Section
4.2
ZL40255 SmartBuffer
TM
3-Output Programmable Fanout Buffer
with Multi-Format I/O and Dividers
Data Sheet
April 2018
Features
•
Four Input Clocks
•
One crystal/CMOS input
•
Two differential/CMOS inputs
•
One single-ended/CMOS input
•
Any input frequency up to 1035MHz (up to
300MHz for CMOS)
•
Clock selection by pin or register control
•
Up to 3 Differential Outputs (Up to 6 CMOS)
•
Output frequencies are any integer divisor up to
2
32
of the input frequency (CMOS 250MHz max)
•
Each output has independent dividers
•
Low additive jitter <200fs RMS (12kHz-20MHz,
for input frequencies
100MHz)
•
Outputs are CML or 2xCMOS, can interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
•
In 2xCMOS mode, the P and N pins can be
different frequencies (e.g. 125MHz and 25MHz)
*
•
Per-output supply pin with CMOS output
voltages from 1.5V to 3.3V
•
Precise output alignment circuitry and per-
output phase adjustment
*
•
Per-output enable/disable and glitchless
start/stop (stop high or low)
*
Ordering Information
ZL40255LDG1
ZL40255LDF1
32 Pin QFN
32 Pin QFN
Matte Tin
Package size: 5 x 5 mm
-40
C to +85
C
Trays
Tape and Reel
•
General Features
•
Automatic self-configuration at power-up from
internal EEPROM; up to four configurations,
pin-selectable
•
Crystal interface for frequency synthesis up to
60MHz
•
Four general-purpose I/O pins, each with many
status and control options
•
SPI or I
2
C processor Interface
•
Tiny 5x5mm QFN package
Applications
•
•
•
Frequency synthesis up to 60MHz
Fanout up to 1035MHz
Format conversion, frequency division, and skew
adjustment in a wide variety of equipment types
Block Diagram
IC1P, IC1N
IC2P, IC2N
IC3P/GPIO3
XA
XB
Application Example 1:
HSDIV1
HSDIV2
HSDIV3
crystal
driver
DIV1
DIV2
DIV3
OC1P, OC1N
VDDO1
OC2P, OC2N
VDDO2
OC3P, OC3N
VDDO3
625MHz
from other
timing IC
156.25MHz differential
ZL40255
125MHz differential
2x 25MHz 1.8V CMOS
Application Example 2:
100MHz
Microprocessor Port
(SPI or I2C Serial)
and HW Control and Status Pins
ZL40255
2x 100MHz differential (HCSL)
2x 50MHz 2.5V CMOS
Application Example 3:
AC0/GPIO0
AC1/GPIO1
TEST/GPIO2
IC3P/GPIO3
RSTN
IF0/CSN
SCL/SCLK
SDA/MOSI
IF1/MISO
2x 50MHz 3.3V CMOS
50MHz
ZL40255
2x 50MHz 1.8V CMOS
2x 25MHz 1.8V CMOS
Figure 1 - Functional Block Diagram and Application Examples
* Some features require a higher-frequency input clock and enabling the output dividers.
1
Microsemi Corporation
Copyright 2018. Microsemi Corporation. All Rights Reserved.
ZL40255
Data Sheet
Table of Contents
1.
2.
3.
3.1
3.2
3.3
3.4
3.5
3.6
PIN DIAGRAM ............................................................................................................................... 4
PIN DESCRIPTIONS ..................................................................................................................... 5
FUNCTIONAL DESCRIPTION ...................................................................................................... 7
D
EVICE
I
DENTIFICATION
................................................................................................................ 7
P
IN
-C
ONTROLLED
A
UTOMATIC
C
ONFIGURATION AT
R
ESET
............................................................. 7
E
XTERNAL
C
RYSTAL AND
O
N
-C
HIP
D
RIVER
C
IRCUIT
....................................................................... 8
I
NPUT
S
IGNAL
F
ORMAT
C
ONFIGURATION
........................................................................................ 8
I
NPUT
S
ELECTION
......................................................................................................................... 9
O
UTPUT
C
LOCK
C
ONFIGURATION
.................................................................................................. 9
Output Enable, Signal Format, Voltage and Interfacing ........................................................................ 9
Output Frequency Configuration ............................................................................................................ 9
Output Duty Cycle Adjustment ............................................................................................................. 10
Output Phase Adjustment and Phase Alignment ................................................................................. 10
Output Clock Start and Stop ................................................................................................................ 13
SPI Slave ............................................................................................................................................. 14
I
2
C Slave .............................................................................................................................................. 16
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.7
M
ICROPROCESSOR
I
NTERFACE
................................................................................................... 14
3.7.1
3.7.2
3.8 I
NTERRUPT
L
OGIC
...................................................................................................................... 18
3.9 R
ESET
L
OGIC
............................................................................................................................. 18
3.10
P
OWER
-S
UPPLY
C
ONSIDERATIONS
.......................................................................................... 19
3.11
A
UTO
-C
ONFIGURATION FROM
EEPROM .................................................................................. 19
3.11.1
3.11.2
Factory-Default Device Configurations ................................................................................................ 19
Direct EEPROM Write Mode ................................................................................................................ 19
3.12
4.
P
OWER
S
UPPLY
D
ECOUPLING AND
L
AYOUT
R
ECOMMENDATIONS
............................................... 19
REGISTER DESCRIPTIONS ....................................................................................................... 19
4.1 R
EGISTER
T
YPES
....................................................................................................................... 20
4.1.1
4.1.2
4.1.3
Status Bits ............................................................................................................................................ 20
Configuration Fields ............................................................................................................................. 20
Bank-Switched Registers ..................................................................................................................... 20
4.2
4.3
R
EGISTER
M
AP
.......................................................................................................................... 20
R
EGISTER
D
EFINITIONS
.............................................................................................................. 22
Global Configuration Registers ............................................................................................................ 22
Status Registers ................................................................................................................................... 28
Source Selection Configuration Registers ........................................................................................... 33
Output Clock Configuration Registers .................................................................................................. 34
Input Clock Configuration Registers .................................................................................................... 38
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
5.
6.
ELECTRICAL CHARACTERISTICS ........................................................................................... 39
PACKAGE AND THERMAL INFORMATION .............................................................................. 49
6.1 P
ACKAGE
T
OP
M
ARK
F
ORMAT
..................................................................................................... 49
6.2 T
HERMAL
S
PECIFICATIONS
.......................................................................................................... 50
MECHANICAL DRAWING .......................................................................................................... 51
ACRONYMS AND ABBREVIATIONS ......................................................................................... 52
DATA SHEET REVISION HISTORY ........................................................................................... 52
7.
8.
9.
2
Microsemi Corporation
ZL40255
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram and Application Examples ................................................................................. 1
Figure 2 - Pin Diagram ................................................................................................................................................. 4
Figure 3 - Crystal Equivalent Circuit / Recommended Crystal Circuit ......................................................................... 8
Figure 4 - SPI Read Transaction Functional Timing.................................................................................................. 15
Figure 5 - SPI Write Enable Transaction Functional Timing ..................................................................................... 15
Figure 6 - SPI Write Transaction Functional Timing .................................................................................................. 16
Figure 7 – I
2
C Read Transaction Functional Timing .................................................................................................. 17
Figure 8 – I
2
C Register Write Transaction Functional Timing ................................................................................... 17
Figure 9 – I
2
C EEPROM Write Transaction Functional Timing ................................................................................. 17
Figure 10 – I
2
C EEPROM Read Status Transaction Functional Timing .................................................................... 17
Figure 11 – Interrupt Structure ................................................................................................................................... 18
Figure 12 - Electrical Characteristics: Clock Inputs ................................................................................................... 41
Figure 13 - Example External Components for Differential Input Signals ................................................................. 42
Figure 14 - Electrical Characteristics: CML Clock Outputs........................................................................................ 43
Figure 15 – Example External Components for CML Output Signals ....................................................................... 43
Figure 16 – Example External Components for HCSL Output Signals ..................................................................... 44
Figure 17 - SPI Slave Interface Timing ...................................................................................................................... 46
Figure 18 - I
2
C Slave Interface Timing ....................................................................................................................... 48
Figure 19 - Device Top Mark ..................................................................................................................................... 49
List of Tables
Table 1 - Pin Descriptions ............................................................................................................................................ 5
Table 2 - Crystal Selection Parameters ....................................................................................................................... 8
Table 3 – SPI Commands .......................................................................................................................................... 14
Table 4 - Register Map .............................................................................................................................................. 20
Table 5 - Recommended DC Operating Conditions .................................................................................................. 39
Table 6 - Electrical Characteristics: Supply Currents ................................................................................................ 39
Table 7 - Electrical Characteristics: Non-clock CMOS Pins ...................................................................................... 40
Table 8 - Electrical Characteristics: XA Clock Input .................................................................................................. 40
Table 9 - Electrical Characteristics: Clock Inputs, ICxP/N ......................................................................................... 41
Table 10 - Electrical Characteristics: CML Clock Outputs ......................................................................................... 42
Table 11 - Electrical Characteristics: CMOS and HSTL (Class I) Clock Outputs ...................................................... 44
Table 12 - Electrical Characteristics: Jitter and Skew Specifications ........................................................................ 45
Table 13 - Electrical Characteristics: SPI Slave Interface Timing, Device Registers ................................................ 46
Table 14 - Electrical Characteristics: SPI Slave Interface Timing, Internal EEPROM .............................................. 47
Table 15 - Electrical Characteristics: I
2
C Slave Interface Timing .............................................................................. 48
Table 16 – Package Top Mark Legend ..................................................................................................................... 49
Table 17 - 5x5mm QFN Package Thermal Properties .............................................................................................. 50
3
Microsemi Corporation
ZL40255
1. Pin Diagram
The device is packaged in a 5x5mm 32-pin QFN.
TEST/GPIO2
Data Sheet
AC0/GPIO0
AC1/GPIO1
SCL/SCLK
DVDD18
IF0/CSN
32
31
30
29
28
27
26
25
24
23
22
21
20
19
IF1/MISO
SDA/MOSI
DVDD33
IC3/GPIO3
IC2N
IC2P
IC1N
IC1P
VDDO1
RSTN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND (E-pad)
OC1P
OC1N
AVDD33
OC2N
OC2P
VDDO2
AVDD18
AVDD18
18
17
XA
XB
VDDXO33
AVDD18
AVDD18
OC3P
Figure 2 - Pin Diagram
4
Microsemi Corporation
VDDO3
OC3N
ZL40255
2. Pin Descriptions
Data Sheet
All device inputs and outputs are LVCMOS unless described otherwise. The Type column uses the following
symbols: I – input, I
PU
– input with 50k internal pullup resistor, O – output, A – analog, P – power supply pin. All
GPIO and SPI/I
2
C interface pins have Schmitt-trigger inputs and have output drivers that can be disabled (high
impedance).
Table 1 - Pin Descriptions
Pin #
Name
Type
Description
Input Clock Pins
Differential or Single-ended signal format. Programmable frequency.
Differential:
See
Table 9
for electrical specifications, and see
Figure 13
for
recommended external circuitry for interfacing these differential inputs to
LVDS, LVPECL, CML or HSCL output pins on neighboring devices.
Single-ended:
For input signal amplitude >2.5V, connect the signal directly to
ICxP pin. For input signal amplitude ≤2.5V, AC-coupling the signal to ICxP
is recommended. Connect the N pin to a capacitor (0.1F or 0.01F) to
VSS. As shown in
Figure 13
, the ICxP and ICxN pins are internally biased to
approximately 1.3V. Treat the ICxN pin as a sensitive node; minimize stubs;
do not connect to anything else including other ICxN pins.
Unused:
Set
ICEN.ICxEN=0.
The ICxP and ICxN pins can be left floating.
Note that the IC3N pin is not bonded out. A differential signal can be
connected to IC3P by AC-coupling the POS trace to IC3P and terminating the
signal on the driver side of the coupling cap. If not needed as an input clock
pin, IC3P can behave as general-purpose I/O pin GPIO3, which is configured
by
GPIOCR2.
Its state is indicated in
GPIOSR.
Crystal or Input Clock Pins
Crystal:
MCR1.XAB=01.
An on-chip crystal driver circuit is designed to work
with an external crystal connected to the XA and XB pins. See section
3.3
for crystal characteristics and recommended external components.
Input Clock:
MCR1.XAB=10.
An external local oscillator or clock signal can be
connected to the XA pin. The XB pin must be left unconnected.
Output Clock Pins
CML, HSTL or 1 or 2 CMOS. Programmable frequency and drive strength.
See
Table 10
and
Figure 15
for electrical specifications and recommended
external circuitry for interfacing to LVDS, LVPECL or CML input pins on
neighboring devices.
See
Table 11
for electrical specifications for interfacing to CMOS and HSTL
inputs on neighboring devices.
See
Figure 16
for recommended external circuitry for interfacing to HCSL inputs
on neighboring devices.
Reset (Active Low)
When this global asynchronous reset is pulled low, all internal circuitry is reset
to default values. The device is held in reset as long as RSTN is low. See
section
3.9.
8
7
6
5
4
IC1P
IC1N
IC2P
IC2N
IC3P/GPIO3
I
I
I
I
I/O
10
11
XA
XB
A/I
24
23
20
21
15
14
OC1P
OC1N
OC2P
OC2N
OC3P
OC3N
O
30
RSTN
I
PU
5
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