CYP15G0402DXB
CYV15G0402DXB
Quad HOTLink II™ SERDES
Features
•
•
•
•
•
•
•
•
•
Second-generation HOTLink
®
technology
Fibre Channel- and Gigabit Ethernet-compliant
ESCON
®
, DVB-ASI-compliant
SMPTE-292M-, SMPTE-259M-compliant
10-bit unencoded data transport
— Aggregate throughput of 12 GBps
Selectable parity check/generate
Four independently controlled 10-bit channels
Selectable input clocking options
MultiFrame™ Receive Framer provides alignment to
— Comma or full K28.5 detect
— Single or multi-byte framer for byte alignment
•
•
•
•
•
•
— Low-latency option
Synchronous LVTTL parallel input interface
Synchronous LVTTL parallel output interface
195-to-1500 MBaud serial signaling rate
Internal phase-locked loops (PLLs) with
no
external
PLL components
Differential PECL-compatible serial inputs
Differential PECL-compatible serial outputs
—
Source matched for 50Ω transmission lines
— No external resistors required
— Signaling-rate controlled edge-rates
• Compatible with
— Fiber-optic modules
— Copper cables
— Circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
Independent
Channel
Transceiver
Independent
Channel
Transceiver
Independent
Channel
Transceiver
Independent
Channel
Transceiver
10
10
• Per-channel Link Quality Indicator
— Analog signal detect
•
•
•
•
— Digital signal detect
Low-power 2.5W @3.3V typical
Single 3.3V supply
256-ball thermally enhanced BGA
0.25µ BiCMOS technology
Functional Description
The CYP(V)15G0402DXB Quad HOTLink II™ SERDES is a
point-to-point communications building block allowing the
transfer of preencoded data over high-speed serial links
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195 to 1500 MBaud per
serial link.
Each transmit channel accepts preencoded 10-bit trans-
mission characters in an Input Register, serializes each
character, and drives it out a PECL-compatible differential line
driver. Each receive channel accepts a serial data stream at a
differential line receiver, deserializes the stream into 10-bit
characters, frames these characters to the proper 10-bit
character boundaries and presents these characters to an
Output register.
Figure 1
illustrates typical connections
between independent systems and a CYP(V)15G0402DXB .
The CYV15G0402DXB satisfies the SMPTE-259M and
SMPTE-292M compliance as per the EG34-1999 Pathological
Test Requirements.
10
Serial Links
System Host With Encoder/Decoder
Note:
1. CYV15G0402DXB refers to the SMPTE compliant parts. CYP15G0402DXB refers to the non-video part.
CYP(V)15G0402DXB corresponds to both the video and non-video parts of the transceiver.
Cypress Semiconductor Corporation
Document #: 38-02057 Rev. *E
System Host With Encoder/Decoder
10
10
10
CYP(V)15G0402DXB
10
10
Serial Links
10
10
10
10
Serial Links
10
10
10
10
Serial Links
Cable or
Optical
Connections
Figure 1. CYP(V)15G0402DXB HOTLink II™ System Connections
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised July 09, 2003
CYP15G0402DXB
CYV15G0402DXB
As
a
second-generation
HOTLink
device,
the
CYP(V)15G0402DXB extends the HOTLink family to faster
data rates, while maintaining serial link compatibility (data,
command and BIST) with other HOTLink devices.The transmit
(TX) section of the CYP(V)15G0402DXB Quad HOTLink II
SERDES consists of four ten bit wide channels that accept a
preencoded character on every clock cycle. Transmission
characters are passed from the Transmit Input Register to a
Serializer. The serialized characters are output from a differ-
ential transmission line driver at a bit-rate of 10 or 20 times the
input reference clock.
The receive (RX) section of the CYP(V)15G0402DXB Quad
HOTLink II SERDES consists of four ten bit wide channels.
Each channel accepts a serial bit-stream from a
PECL-compatible differential line receiver and, using a
completely integrated PLL Clock Synchronizer, recovers the
timing information necessary for data reconstruction. Each
recovered bit-stream is deserialized and framed into
characters. Recovered characters are then passed to the
receiver output register, along with a recovered character
clock.
The parallel I/O interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture. In addition to clocking the transmit path, the
receive interface may be configured to present data relative to
a recovered clock or to a local reference clock.
Each transmit and receive channel contains an independent
BIST pattern generator and checker. This BIST hardware
allows at-speed testing of the interface data path.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point serial links. Some applications include intercon-
necting backplanes on switches, routers, servers and video
transmission systems
CYV15G0402DXB is tested for the pathological test patterns
for SMPTE-259 and SMPTE-292M compliance as per the
EG34-1999 Pathological Test Requirements. The test is done
for the following patterns.
1. Screen parts at the required pattern of 20 high and 20 low
bits continuously for burst of 20.
2. Screen parts at a single burst of 44 low or high periods.
3. Screen parts at a pattern of 19 high and 1 low or 19 low and
1 high bit for a pattern of 20.
CYP(V)15G0402DXB Transceiver Logic Block Diagram
RXDB[9:0]
RXDC[9:0]
RXDA[9:0]
RXDD[9:0]
TXDB[9:0]
TXDA[9:0]
TXDC[9:0]
TXDD[9:0]
x10
x10
x10
x10
x10
x10
x10
x10
Phase
Align
Buffer
Serializer
Framer
Deserializer
Phase
Align
Buffer
Serializer
Framer
Phase
Align
Buffer
Serializer
Framer
Deserializer
Phase
Align
Buffer
Serializer
Framer
Deserializer
Deserializer
TX
RX
TX
RX
TX
RX
TX
RX
OUTA±
INA±
OUTB±
INB±
OUTC±
INC±
OUTD±
Document #: 38-02057 Rev. *E
Page 2 of 28
IND±
CYP15G0402DXB
CYV15G0402DXB
Transmit Path Block Diagram
REFCLK+
REFCLK–
= Internal Signal
TXRATE
SPDSEL
TXCLKO+
TXCLKO–
Transmit PLL
Clock Multiplier
Character-Rate Clock
Bit-Rate Clock
BISTLE
BIST Enable
Latch
Output
Enable
Latch
8
Phase-Align
Buffer
BOE[7..0]
RBIST[A..D]
OELE
TXCKSEL
TXPERA
Input
Register
11
11
11
BIST LFSR
4
TXDA[0..9]
TXOPA
Shifter
Parity
Check
10
OUTA+
OUTA–
H M L
TXLBA
TXCLKA
TXPERB
Phase-Align
Buffer
BIST LFSR
Input
Register
Shifter
Parity
Check
TXDB[0..9]
TXOPB
11
11
11
10
OUTB+
OUTB–
H M L
TXLBB
TXCLKB
TXPERC
Phase-Align
Buffer
Input
Register
Shifter
Parity
Check
11
11
11
BIST LFSR
10
OUTC+
OUTC–
TXDC[0..9]
TXOPC
H M L
TXLBC
TXCLKC
TXPERD
Phase-Align
Buffer
BIST LFSR
Input
Register
Shifter
Parity
Check
TXDD[0..9]
TXOPD
11
11
11
10
OUTD+
OUTD–
H M L
TXLBD
TXCLKD
TXRST
PARCTL
Document #: 38-02057 Rev. *E
Parity Control
Page 3 of 28
CYP15G0402DXB
CYV15G0402DXB
Receive Path Block Diagram
RXLE
BOE[7:0]
RX PLL Enable
Latch
= Internal Signal
TRSTZ
TMS
TCLK
TDI
TDO
LFIA
BIST
LFSR
Output
Register
Framer
Parity Control
Character-Rate Clock
SDASEL
LPENA
INA+
INA–
JTAG
Boundary
Scan
Controller
Receive
Signal
Monitor
Clock and
Data
Recovery
PLL
Shifter
RXDA[0..9]
RXOPA
COMDETA
TXLBA
RFENA
LPENB
÷2
Receive
Signal
Monitor
Framer
Shifter
Clock and
Data
Recovery
PLL
RXCLKA+
RXCLKA–
LFIB
BIST
LFSR
Output
Register
RXDB[0..9]
RXOPB
COMDETB
INB+
INB–
TXLBB
RFENB
LPENC
÷2
Receive
Signal
Monitor
Framer
Clock and
Data
Recovery
PLL
Shifter
RXCLKB+
RXCLKB–
LFIC
BIST
LFSR
Output
Register
RXDC[0..9]
RXOPC
COMDETC
INC+
INC–
TXLBC
RFENC
LPEND
÷2
Receive
Signal
Monitor
Clock and
Data
Recovery
PLL
RBIST[A..D]
Framer
Shifter
RXCLKC+
RXCLKC–
LFID
BIST
LFSR
Output
Register
RXDD[0..9]
RXOPD
COMDETD
IND+
IND–
TXLBD
RFEND
FRAMCHAR
RXRATE
RFMODE
÷2
RXCLKD+
RXCLKD–
Document #: 38-02057 Rev. *E
Page 4 of 28
CYP15G0402DXB
CYV15G0402DXB
Pin Configuration
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
2
3
N/C
N/C
4
N/C
N/C
5
V
CC
V
CC
6
7
8
9
N/C
N/C
10
N/C
N/C
11
12
13
14
N/C
N/C
GND
GND
15
N/C
N/C
GND
GND
16
V
CC
V
CC
17
18
19
N/C
20
N/C
N/C
TDO
N/C
V
CC
INC- OUTC-
INC+ OUTC
+
TDI
IND- OUTD-
GND
IND+ OUTD
GND
+
INA- OUTA-
GND
INA+ OUTA+
GND
INB- OUTB-
INB+ OUTB+ N/C
TMS LPENC LPENB
V
CC
PARCTLSDASEL
GND
BOE[7] BOE[5] BOE[3] BOE[1]
GND
RF SPDSEL
GND
BOE[6] BOE[4] BOE[2] BOE[0]
GND
MODE
V
CC
TXRATERXRATE N/C
V
CC
N/C
V
CC
RXLE
V
CC
N/C
V
CC
TCLK TRSTZ LPEND LPENA
V
CC
V
CC
V
CC
V
CC
V
CC
TXPERC TXOPC TXDC[0] N/C
TXDC[7] TXCKSE TXDC[4] TXDC[1]
L
GND
GND
GND
GND
BISTLE RXDB[0] RXOPB RXDB[1]
GND
GND
OELE FRAM RXDB[3]
CHAR
GND
GND
GND
TXDC[9] TXDC[5] TXDC[2} TXDC[3]
RXDC[4]RXCLKC TXDC[8] LFIC
-
RXDC[5]RXCLKCTXCLKC TXDC[6]
+
RXDC[6] RXDC[7] RXDC[9] RXDC[8]
GND
GND
GND
GND
COMDE RXDB[2] RXDB[7] RXDB[4]
TB
RXDB[5] RXDB[6] RXDB[9] RXCLKB
+
RXDB[8] LFIB RXCLKB TXDB[6]
-
TXDB[9] TXDB[8] TXDB[7] TXCLKB
GND
GND
GND
GND
RXDC[3] RXDC[2] RXDC[1] RXDC[0]
COMDE RXOPC TXPERD TXOPD
TC
V
CC
V
CC
V
CC
V
CC
TXDB[5] TXDB[4] TXDB[3] TXDB[2]
TXDB[1] TXDB[0] TXOPB TXPERB
V
CC
V
CC
V
CC
V
CC
TXDD[0] TXDD[1] TXDD[2] TXDD[9] VCC RXDD[4] RXDD[3] GND RXOPD RFENC REFCLK TXDA[1] GND TXDA[4] TXDA[8] VCC RXDA[4] RXOPA COMDE RXDA[0]
-
TA
TXDD[3] TXDD[4] TXDD[8] RXDD[8] VCC RXDD[5] RXDD[1] GND COMDE RFEND REFCLK RFENB
TD
+
TXDD[5] TXDD[7] LFID RXCLKD VCC RXDD[6] RXDD[0] GND TXCLKO TXRST TXOPA RFENA
–
–
TXDD[6] TXCLKD RXDD[9]RXCLKD VCC RXDD[7] RXDD[2] GND TXCLKO
+
+
N/C
GND TXDA[3] TXDA[7] VCC RXDA[9] RXDA[5] RXDA[2] RXDA[1]
GND TXDA[2] TXDA[6] VCC
LFIA RXCLKA RXDA[6] RXDA[3]
–
TXCLKATXPERA GND TXDA[0] TXDA[5] VCC TXDA[9] RXCLKA RXDA[8] RXDA[7]
+
Document #: 38-02057 Rev. *E
Page 5 of 28
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