P2042A
Product Preview
LCD Panel EMI Reduction IC
Product Description
The P2042A is a versatile spread spectrum frequency modulator
designed specifically for digital flat panel applications. The P2042A
reduces electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of down stream clock and data
dependent signals. The P2042A allows significant system cost savings
by reducing the number of circuit board layers, ferrite beads,
shielding, and other passive components that are traditionally required
to pass EMI regulations.
The P2042A uses the most efficient and optimized modulation
profile approved by the FCC and is implemented in a proprietary all
digital method.
The P2042A modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, and more importantly,
decreases the peak amplitudes of its harmonics. This results in
significantly lower system EMI compared to the typical narrow band
signal produced by oscillators and most frequency generators.
Lowering EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Applications
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SOIC−8
S SUFFIX
CASE 751BD
TSSOP−8
T SUFFIX
CASE 948AL
PIN CONFIGURATION
CLKIN
CP0
CP1
VSS
(Top View)
1
VDD
P2042A
SR0
ModOUT
SSON#
The P2042A is targeted towards digital flat panel applications for
notebook PCs, palm−size PCs, office automation equipments, and
LCD monitors.
Features
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
•
FCC Approved Method of EMI Attenuation
•
Provides up to 15 dB of EMI Suppression
•
Generates a Low EMI Spread Spectrum Clock of the Input
•
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•
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Frequency
Input Frequency Range: 30 MHz to 110 MHz
Optimized for 32.5 MHz, 54 MHz, 65 MHz and 108 MHz Pixel
Clock Frequencies
Internal Loop Filter Minimizes External Components and Board
Space
Eight Selectable High Spread Ranges up to
±1.9%
SSON# Control Pin for Spread Spectrum Enable and Disable Options
Low Cycle−to−Cycle Jitter
3.3 V
±
0.3 V Operating Range
Low Power CMOS Design
Supports Most Mobile Graphic Accelerator and LCD Timing
Controller Specifications
Available in 8−pin SOIC and TSSOP Packages
These are Pb−Free Devices
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. P3
1
Publication Order Number:
P2042A/D
P2042A
SR0 CP1 CP0 SSON#
VDD
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Figure 1. Block Diagram
Table 1. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Parameter
Voltage on any pin with respect to Ground
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Rating
−0.5
to +4.6
−65
to +125
−40
to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 2. PIN DESCRIPTION
Pin#
1
2
3
4
5
Pin Name
CLKIN
CP0
CP1
VSS
SSON#
Type
I
I
I
P
I
Description
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select charge pump current. This pin has an internal pull−up resistor.
Refer to
Modulation Selection
Table.
Digital logic input used to select charge pump current. This pin has an internal pull−up resistor.
Refer to
Modulation Selection
Table.
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function
enabled when LOW, disabled when HIGH.
This pin has an internal pull−low resistor.
Spread spectrum clock output.
Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor.
Power supply for the entire chip
6
7
8
ModOUT
SR0
VDD
O
I
P
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2
P2042A
Table 3. MODULATION SELECTION
Spreading Range (+%)
CP0
0
0
0
0
1
1
1
1
CP1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
32.5 MHz
0.56
1.94
1.36
1.92
1.24
1.91
0.91
1.47
54 MHz
1.05
1.68
1.05
1.68
0.81
1.29
0.45
0.71
65 MHz
1.00
1.56
1.00
1.56
0.66
1.02
0.34
0.54
81 MHz
0.98
1.48
0.92
1.48
0.40
0.74
0.05
0.36
108 MHz
0.80
1.22
0.67
1.06
0.27
0.43
0.15
0.21
(FIN /40) * 62.49 KHz
Modulation Rate (KHz)
Spread Spectrum Selection
The
Modulation Selection
Table defines the possible
spread spectrum options. The optimal setting should
minimize system EMI to the fullest without affecting system
performance. The spreading is described as a percentage
deviation of the center frequency. (Note: The center
frequency is the frequency of the external reference input on
CLKIN, pin1).
For example, P2042A is designed for high−resolution, flat
panel applications and is able to support an XGA (1024 x
768) flat panel operating at 65 MHz (FIN) clock speed. A
spreading selection of CP0 = 0, CP1 = 1 and SR0 = 0
provides a percentage deviation of
±1.00%
from F
IN
. This
results in the frequency on ModOUT being swept from
65.65 to 64.35 MHz at a modulation rate of 101.54 KHz.
Refer to
Modulation Selection
Table. The example in the
following illustration is a common EMI reduction method
for a notebook LCD panel and has already been
implemented by most of the leading OEM and mobile
graphic accelerator manufacturers.
+3.3 V
Modulated 65 MHz signal with
±1.00%
deviation and modulation
rate of 101.54 KHz. This signal is
connected back to the spread
spectrum input pin (SSIN) of the
graphics accelerator.
65 MHz from graphics accelerator
1 CLKIN
2 CP0
3 CP1
4 VSS
VDD 8
SR0 7
ModOUT 6
0.1
mF
SSON# 5
P2042A
Digital control for the SS enable
or disable.
Figure 2. Application Schematic for Mobile LCD Graphics Controllers
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3
P2042A
Table 4. OPERATING CONDITIONS
Symbol
VDD
T
A
T
J
Parameter
Supply Voltage with respect to Ground
Operating temperature
Commercial
Industrial
Junction temperature
Commercial
SOIC
TSSOP
Industrial
SOIC
TSSOP
q
JC
SOIC
TSSOP
156.5
124
Min
3.0
0
−40
Typ
3.3
Max
3.6
+70
+85
82.39
79.8
97.39
94.8
°C/W
°C
Unit
V
°C
Table 5. DC ELECTRICAL CHARACTERISTICS
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
(pull−up resistor on inputs CP0, CP1 and SR0)
Input high current (pull−down resistor on input SSON#)
Output low voltage (V
DD
= 3.3 V, I
OL
= 20 mA)
Output high voltage (V
DD
= 3.3 V, I
OL
= 20 mA)
Static supply current standby mode
Dynamic supply current (3.3 V and 10 pF loading)
Operating voltage
Power−up time (first locked cycle after power up)
Clock output impedance
9
3.0
2.5
0.6
16
3.3
0.18
50
22
3.6
Parameter
Min
VSS−0.3
2.0
Typ
Max
0.8
VDD+0.3
−35
35
0.4
Unit
V
V
mA
mA
V
V
mA
mA
V
mS
W
Table 6. AC ELECTRICAL CHARACTERISTICS
Symbol
f
IN
f
OUT
t
LH
(Note 1)
t
HL
(Note 1)
t
JC
t
D
Input frequency
Output frequency
Output rise time (measured at 0.8 V to 2.0 V)
Output fall time (measured at 2.0 V to 0.8 V)
Jitter (cycle−to−cycle)
Output duty cycle
45
50
Parameter
Min
30
30
0.7
0.6
Typ
65
65
0.9
0.8
Max
110
110
1.1
1.0
360
55
Unit
MHz
MHz
nS
nS
pS
%
1. t
LH
and t
HL
are measured into a capacitive load of 15 pF.
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4
P2042A
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
A
A1
A2
b
E1
E
c
D
E
E1
e
L
L1
MIN
0.05
0.80
0.19
0.09
2.90
6.30
4.30
NOM
MAX
1.20
0.15
0.90
1.05
0.30
0.20
3.00
6.40
4.40
0.65 BSC
1.00 REF
3.10
6.50
4.50
0.50
0.60
0.75
θ
e
0º
8º
TOP VIEW
D
A2
A
q1
c
A1
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
L1
END VIEW
L
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