© 2013 Rochester Electronics, LLC. All Rights Reserved 04112013
EP610
Features
High-performance, 16-macrocell Classic EPLD
- Combinatorial speeds with t
PD
as low as 10 ns
- Counter frequencies of up to 100 MHz
- Pipelined data rates of up to 100 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs
and 2 Clock pins
The following devices are pin-, function-, and programming
file-compatible: EP610, EP610I, EP610T, EP610-XX/B, EP600I, and
PALCE610
Programmable Clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in windowed ceramic and one-time-programmable (OTP)
plastic packages (see Figure 1):
- 24-pin small-outline integrated circuit (plastic SOIC only)
- 24-pin dual in-line package (CerDIP and PDIP)
- 28-pin plastic J-lead chip carrier (PLCC)
Figure 1. EP610 Package Pin-Out Diagrams
Package outlines not drawn to scale. Windows in ceramic packages only.
INPUT
INPUT
27
CLK1
VCC
VCC
I/O
I/O
26
25
24
23
22
21
20
19
12
I/O
13
INPUT
14
GND
15
GND
16
CLK2
17
INPUT
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
CLK1
INPUT
I/O
CLK1
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
GND
1•
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
CLK2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
CLK2
NC
11
I/O
I/O
I/O
I/O
7
8
9
10
I/O
I/O
5
6
4
3
2
1
28
24-Pin SOIC
EP610
EP610T
24-Pin DIP
EP610
EP610T
EP610-XX/B
EP610I
28-Pin J-Lead
EP610
EP610T
EP610I
For complete Rochester ordering guide, please refer to page 2
Please contact factory for specific package availability and
Military/Aerospace specifications/availability.
Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes
only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves
the right to make changes without further notice to any specification herein.
Specification Number EP610-CI (AT) REV -
Page 1 of 9
EP610
Table 1 summarizes EP610 device features
Table 1. EP610 Device Features
Feature
t
PD
Counter frequency
Pipeline data rates
Packages
15 ns
83 MHz
83 MHz
24-pin SOIC
24-pin CerDIP
24-pin PDIP
24-pin PLCC
EP610
15 ns
EP610T
83 MHz
83 MHz
24-pin SOIC
24-pin PDIP
28-pin PLCC
EP610-XX/B
35 ns
28.5 MHz
37 MHz
24-pin CerDIP
10 ns
EP610I
100 MHz
100 MHz
24-pin CerDIP
24-pin PDIP
28-pin PLCC
General
Description
EP610 devices have 16 macrocells, 4 dedicated input pins, 16
I/O pins, and 2 global Clock pins (see Figure 2). Each macrocell
can access signals from the global bus, which consists of the
true and complement forms of the dedicated inputs and the
true complement forms of either the output of the macrocell of
the I/O input. CLK1 is a dedicated Clock input for the registers
in macrocells 9 through 16. CLK2 is a dedicated Clock input for
registers in macrocells 1 through 8.
Figure 2. EP610 Block Diagram
Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages.
2 (3) INPUT
1 (2)
CLK1
INPUT 23 (27)
CLK2
13 (16)
3 (4)
4 (5)
5 (6)
6 (7)
7 (8)
8 (9)
9 (10)
10 (12)
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Global
Bus
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
22 (26)
21 (25)
20 (24)
19 (23)
18 (22)
17 (21)
16 (20)
15 (18)
11 (13) INPUT
INPUT 14 (17)
Specification Number EP610-CI (AT) REV -
Page 3 of 9
EP610
Absolute Maximum Ratings
EP610
EP610T
EP610-XX/B
Symbol
V
CC
V
I
I
MAX
I
OUT
P
D
T
STG
T
AMB
T
J
EP610I
Min Max Unit
-2.0
-0.5
7.0
V
CC
+
0.5
V
V
mA
mA
mW
-65
-10
150
85
°C
°C
°C
Parameter
Supply voltage
DC input voltage
DC VCC or GND current
DC output current, per pin
Power dissipation
Storage temperature
Ambient temperature
Junction temperature
Conditions
With respect
to GND
Min
-2.0
-2.0
-175
-25
Max
7.0
7.0
175
25
1000
150
135 (125)
(150)
No bias
Under bias
Under bias
-65
-65
Recommended Operating Conditions
EP610
EP610T
EP610-XX/B
Symbol
V
CC
V
I
V
O
T
A
T
A
T
C
t
R
t
F
EP610I
Min Max Unit
4.75
0
0
0
-40
5.25
V
CC
V
CC
70
85
500
500
V
V
V
°C
°C
°C
ns
ns
Parameter
Supply voltage
Input voltage
Output voltage
Operating Temperature
Operating Temperature
Case Temperature
Input rise time
Input fall time
Conditions
Min
4.75 (4.5)
0
0
Max
5.25 (5.5)
V
CC
V
CC
70
85
125
100 (50)
100 (50)
For commerical use
For industrial use
For military use
0
-40
-55
Recommended Operating Conditions
Symbol
V
IH
V
IL
V
OH
V
OH
V
OL
I
I
I
OZ
Parameter
High-level input voltage
Low-level input voltage
High-level TTL output voltage
High-level CMOS output voltage
Low-level output voltage
Input leakage output
Tri-state output leakage current
Conditions
Min
2.0
-0.3
Typ
Max
V
CC
+ 0.3
0.8
Unit
V
V
V
V
I
OH
= -4 mA DC
I
OH
= -2 mA DC
I
OL
= 4 mA DC
V
I
= V
CC
or GND
V
O
= V
CC
or GND
2.4
3.84
0.45
-10
-10
10
10
V
µA
µA
Specification Number EP610-CI (AT) REV -
Page 4 of 9
Linux and Android
京公网安备 11010802033920号
EEWORLD
