PIC24FJ64GA004 FAMILY
PIC24FJ64GA004 Family
Silicon Errata and Data Sheet Clarification
The PIC24FJ64GA004 family devices that you have
received conform functionally to the current Device Data
Sheet (DS39881E), except for the anomalies described
in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC24FJ64GA004 family
silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2
apply to the current silicon
revision (B8).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1.
Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
From the main menu in MPLAB IDE, select
Configure>Select Device,
and then select the
target part number in the dialog box.
Select
the
MPLAB
hardware
tool
(Debugger>Select
Tool).
Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number
and
Device
Revision ID value appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
2.
3.
4.
Data Sheet clarifications and corrections start on
Page 20,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
The DEVREV values for the various PIC24FJ64GA004
family silicon revisions are shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
Device ID
(1)
A3/A4
044Fh
044Eh
044Dh
044Ch
0447h
0446h
0445h
0444h
3003h
3042h
3043h
3046h
Revision ID for Silicon Revision
(2)
B4
B5
B8
Part Number
PIC24FJ64GA004
PIC24FJ48GA004
PIC24FJ32GA004
PIC24FJ16GA004
PIC24FJ64GA002
PIC24FJ48GA002
PIC24FJ32GA002
PIC24FJ16GA002
Note 1:
2:
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
Refer to the
“PIC24FJXXXGA0XX Flash Programming Specification”
(DS39768) for detailed information
on Device and Revision IDs for your specific device.
2009-2013 Microchip Technology Inc.
DS80000470H-page 1
PIC24FJ64GA004 FAMILY
TABLE 2:
Module
JTAG
LVD
Core
Core
Core
Core
A/D
A/D
A/D
I
2
C
UART
UART
UART
UART
UART
UART
SILICON ISSUE SUMMARY
Feature
—
—
Idle mode
Doze mode
BOR
RAM
—
—
—
SDA Line
State (I2C1)
—
—
Auto-Baud
Auto-Baud
Auto-Baud
Break
Character
Generation
—
Enhanced
Buffer mode
—
Enhanced
Buffer mode
—
—
—
Item
Number
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Affected Revisions
(1)
Issue Summary
A3/A4
Persistent pull-up (RA3) when JTAG
disabled.
No LVD interrupt with low-voltage condition
at Reset.
Clock failure trap fails in Idle mode.
RAM read repeats on entering Doze mode.
POR and BOR flags both set on BOR.
RAM size implementation on some devices.
Unimplemented channels may be selected.
Missing midscale conversion code.
Device may not wake when convert on INT0
trigger is selected.
Line state may not be detected correctly.
Reception failures in High-Speed mode.
Erroneous baud rate calculations in
High-Speed mode.
Double receive interrupt with auto-baud
reception.
Insertion of spurious data with auto-baud
reception.
Auto-baud calculation errors causing
transmit or receive failures.
The UARTx module will not generate
back-to-back Break characters.
Single missed compare events under certain
conditions.
Some flag bits are set at incorrect times in
Enhanced Buffer mode.
Module in Slave mode may ignore SSx pin
and receive data anyway.
No SPIx interrupt in Enhanced Buffer mode
under certain conditions.
Spec change for V
OL
and V
OH
.
OSCO/RA3 driven immediately following
POR.
Sync loss in ICSP™ mode.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B4
B5
B8
Output
Compare
SPI
SPI
SPI
I/O
I/O
JTAG
Note 1:
17.
18.
19.
20.
21.
22.
23.
X
X
X
X
X
X
X
Only those issues indicated in the last column apply to the current silicon revision.
DS80000470H-page 2
2009-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 2:
Module
RTCC
I C
I C
UART
I/O
UART
UART
Core
Core
Memory
RTCC
SPI
I
2
C™
PPS
UERIF
Interrupt
FIFO Error
Flags
BOR
Instruction
Set
PSV
—
Master
mode
Master
mode
Slave mode
—
—
SOSC
—
Code-Protect
—
IrDA
®
Doze Mode
2
2
SILICON ISSUE SUMMARY (CONTINUED)
Feature
—
Slave mode
—
IrDA
®
Item
Number
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
Affected Revisions
(1)
Issue Summary
A3/A4
Write errors to ALCFGRPT register.
In Slave mode, ACKSTAT bit state change.
Issues with write operations on I2CxSTAT.
IR baud clock only available during transmit.
Issues with digital signal priorities with RP12
and RP18.
No UERIF flag with multiple errors.
PERR and FERR are not correctly set for all
bytes in receive FIFO.
Spontaneous BOR events with low-range
V
DD
.
Loop count errors with
REPEAT
instruction
and R-A-W stalls.
False address error traps at lower boundary
of PSV space.
Decrement of alarm repeat counter under
certain conditions.
SPIF and SPIBEN may become set early
under certain conditions.
Module may respond to its own master
transmission as a slave under certain
conditions.
Failure to respond correctly to some
reserved addresses in 10-bit mode.
TBF flag not cleared under certain
conditions.
Erroneous sampling and framing errors
when using two Stop bits.
Low-power SOSC unimplemented.
Standby mode not available.
General code protection disables
bootloader functionality.
Interrupts when SPIx is operating in
Enhanced Buffer mode.
RXINV bit operation is inverted in IrDA
®
mode
Instruction execution glitches following
DOZE bit changes.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B4
B5
B8
I
2
C
I
2
C
UART
Oscillator
Voltage
Regulator
Core
SPIx
UART
Core
Note 1:
37.
38.
39.
40.
41.
42.
43.
44.
45.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Only those issues indicated in the last column apply to the current silicon revision.
2009-2013 Microchip Technology Inc.
DS80000470H-page 3
PIC24FJ64GA004 FAMILY
TABLE 2:
Module
SPI
SPI
SPI
Core
I/O Ports
A/D
Converter
UART
I
2
C
Note 1:
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Master
mode
Master
mode
Framed
modes
Data SRAM
PORTA and
PORTB
—
TX Interrupt
SMBus
Item
Number
46.
47.
48.
49.
50.
51.
52.
53.
Affected Revisions
(1)
Issue Summary
A3/A4
Spurious transmission and reception of null
data on wake-up from Sleep (Master mode).
Inaccurate SPITBF flag with high clock
divider.
Framed SPIx modes not supported.
Higher current consumption during SRAM
operations.
Some I/O pin functions do not work correctly
under certain conditions
Once the A/D module is enabled, it may
continue to draw extra current
A TX Interrupt may occur before the data
transmission is complete.
I2C1 may not function when I2C2 is in
SMBus mode.
X
X
X
X
X
B4
X
X
X
X
X
X
X
X
B5
X
X
X
X
X
X
X
X
X
X
X
X
B8
X
X
X
Only those issues indicated in the last column apply to the current silicon revision.
DS80000470H-page 4
2009-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B8).
3. Module: Core
If a clock failure occurs when the device is in Idle
mode, the oscillator failure trap does not vector to
the Trap Service Routine. Instead, the device will
simply wake-up from Idle mode and continue code
execution if the Fail-Safe Clock Monitor (FSCM) is
enabled.
Work around
1. Module: JTAG
When the JTAG is disabled, the pull-up resistor on
the TDI pin (Pin 35/RA9) will stay enabled on the
44-pin variants of the device. This can cause the
device to draw extra current when asleep if the pin
is used as an input and held low.
Work around:
The pin will not draw extra current if any of the
following work around techniques are used:
• The pin is used as an output.
• The pin is driven high as an input.
• JTAG is enabled.
Affected Silicon Revisions
A3/
A4
X
B4
B5
B8
Whenever the device wakes up from Idle (assuming
the FSCM is enabled), the user software should
check the status of the OSCFAIL bit (INTCON1<1>)
to determine whether a clock failure occurred, and
then perform an appropriate clock switch operation.
Affected Silicon Revisions
A3/
A4
X
B4
B5
B8
4. Module: Core
If a RAM read is performed on the instruction
immediately prior to enabling Doze mode, then an
extra read event will occur when Doze mode is
enabled. On most SFRs and on user RAM space,
this will have no visible effect. However, this can
cause registers which perform actions on reads,
such as auto-incrementing or decrementing a
pointer or removing data from a FIFO buffer, to
repeat that action, possibly resulting in lost data.
Work around
On the instruction prior to entering Doze mode, be
sure not to read a register which performs a sec-
ondary action. Examples of this would be UARTx
and SPIx FIFO buffers, and the RTCVAL registers.
The easiest way to ensure this does not occur is to
execute a
NOP
instruction before entering Doze
mode.
Affected Silicon Revisions
2. Module: Low-Voltage Detect (LVD)
The Low-Voltage Detect interrupt will not occur if
the device comes out of Reset in a low-voltage
state. To trigger an interrupt, the voltage must
decrease to a low-voltage range while the device
is running.
Work around
None.
Affected Silicon Revisions
A3/
A4
X
B4
B5
B8
A3/
A4
X
B4
B5
B8
2009-2013 Microchip Technology Inc.
DS80000470H-page 5
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