5 Volt Byte Alterable EEPROM
FT28C512/513
FEATURES
• Access time: 90ns
• Simple byte and page write
—Single 5V supply
• No external high voltages or V
PP
control
circuits
—Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low power CMOS
—Active: 50mA
—Standby: 500µA
• Software data protection
—Protects data against system level inadvertent
writes
• High speed page write capability
• Highly reliable
—Endurance: 100,000 write cycles
—Data retention: 100 years
• Early end of write detection
—DATA polling
—Toggle bit polling
BLOCK DIAGRAM
X Buffers
Latches and
Decoder
• Two PLCC and LCC pinouts
—FT28C512
•
FT28C010
EPROM pin compatible
—FT28C513
• Compatible with lower density EEPROMs
DESCRIPTION
The
FT28C512/513
is a 64K x 8 EEPROM, fabricated
with
Force’s
proprietary, high performance, floating
gate CMOS technology.
The FT28C512/513 is a 5V only
device.
The
FT28C512/513
features the JEDEC
approved pin out for byte wide memories, compatible
with industry standard EPROMS.
The
FT28C512/513
supports a 128-byte page write
operation, effectively providing a 39µs/byte write cycle
and enabling the entire memory to be written in less
than 2.5 seconds. The
FT28C512/513
also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion
of a write cycle. In addition, the
FT28C512/513
supports
the software data protection option.
A
7
–A
15
512Kbit
EEPROM
Array
A
0
–A
6
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
CE
OE
WE
V
CC
V
SS
Control
Logic and
Timing
I/O
0
–I/O
7
Data Inputs/Outputs
Rev A
1/25
2011
FT28C512/513
PIN CONFIGURATIONS
TSOP
A 11
A9
A8
A13
A14
NC
NC
NC
WE
V CC
NC
NC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
A 10
CE
I/O 7
I/O6
I/O 5
I/O 4
I/O 3
NC
NC
V SS
NC
NC
I/O 2
I/O1
I/O 0
A0
A1
A2
A3
PLCC/LCC
A
12
A
15
NC
NC
V
CC
WE
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
30
32 31 29
1
28
6
7
27
26
8
FT28C512
25
9
(Top View)
24
10
11
23
12
22
13 15 16 17 18 19 20
21
14
54 3 2
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
I/O
6
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
I/O
5
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
30
32 31 29
1
28
6
7
27
26
8
FT28C512
9
(Top View)
25
24
10
11
23
12
22
13 15 16 17 18 19 20
21
14
54 3 2
NC
I/O
3
I/O
4
I/O
1
I/O
2
V
SS
Plastic DIP
CERDIP
FLAt Pack
SOIC (R)
NC
NC
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FT28C512
FT28C512
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
NC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
PGA
I/O
0
15
A
1
13
A
2
12
A
4
10
A
6
8
A
12
6
5
NC
4
3
A
0
14
A
3
11
A
5
9
A
7
7
A
15
NC
2
NC
V
CC
36
NC
1
NC
34
WE
35
I/O
2
17
I/O
3
I/O
5
19
21
I/O
6
22
CE
24
OE
26
A
9
28
A
13
30
A
14
31
I/O
4
I/O
1
V
SS
I/O
7
20
16
18
23
A
10
25
A
11
27
A
8
29
NC
32
NC
33
FT28C512
Bottom
View
PIN DESCRIPTIONS
Addresses (A
0
–A
15
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers and is used to initiate read operations.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the
FT28C512/513
through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to
the
FT28C512/513.
PIN NAMES
Symbol
A
0
–A
15
I/O
0
–I/O
7
WE
CE
OE
V
CC
V
SS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
Rev A
2/25
A
7
A
12
A
14
A
15
V
CC
WE
A
13
2011
FT28C512/513
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The
data bus will be in a high impedance state when either
OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The
FT28C512/513
supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 5ms.
Page Write Operation
The page write feature of the
FT28C512/513
allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to
be consecutively written to the
FT28C512/513,
prior to
the commencement of the internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the
source address), but the page address (A
7
through
A
15
) for each subsequent valid write cycle to the part
during this operation must be the same as the initial
page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by
the WE HIGH to LOW transition, must begin within
100µs of the falling edge of the preceding WE. If a sub-
sequent WE HIGH to LOW transition is not detected
within 100µs, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively, the page write window is infinitely
wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
Reserved
Toggle Bit
DATA Polling
Write Operation Status Bits
The
FT28C512/513
provides the user two write opera-
tion status bits. These can be used to optimise a sys-
tem write cycle time. The status bits are mapped onto
the I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
The
FT28C512/513
features DATA polling as a method
to indicate to the host system that the byte write or
page write cycle has completed. DATA Polling allows a
simple bit test operation to determine the status of the
FT28C512/513,
eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
duce the complement of that data on I/O
7
(i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true
data.
Toggle Bit (I/O
6
)
The
FT28C512/513
also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O
6
will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete, the toggling will cease, and the device will
be accessible for additional read or write operations.
DATA Polling (I/O
7
)
Rev A
3/25
2011
FT28C512/513
DATA POLLING I/O
7
Figure 2a. DATA Polling Bus Sequence
Last
Write
WE
CE
OE
V
IH
I/O
7
HIGH Z
V
OL
A
0
–A
15
A
n
A
n
A
n
A
n
A
n
A
n
A
n
V
OH
FT28C512/513
Ready
Figure 2b. DATA Polling Software Flow
Write Data
DATA Polling can effectively halve the time for writing to
the
FT28C512/513.
The timing diagram in Figure 2a
illustrates the sequence of events on the bus. The soft-
ware flow diagram in Figure 2b illustrates one method
of implementing the routine.
Writes
Complete?
Yes
Save Last Data
and Address
No
Read Last
Address
IO
7
Compare?
Yes
No
Ready
Rev A
4/25
2011
FT28C512/513
THE TOGGLE BIT I/O
6
Figure 3a. Toggle Bit Bus Sequence
Last
WE Write
CE
OE
I/O
6
V
OH
*
V
OL
HIGH Z
*
FT28C512/513
Ready
* Beginning and ending state of I/O
6
will vary.
Figure 3b. Toggle Bit Software Flow
Last Write
provide a method for status checking in multiprocessor
applications. The timing diagram in Figure 3a illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3b illustrates a method for polling the
Toggle Bit.
HARDWARE DATA PROTECTION
Load Accum
From Addr N
The
FT28C512/513
provides three hardware features
that protect nonvolatile data from inadvertent writes.
– Noise Protection—A WE pulse typically less than
10ns will not initiate a write cycle.
Compare
Accum with
Addr N
– Default V
CC
Sense—All write functions are inhibited
when V
CC
is 3.6V.
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle dur-
ing power-up and power-down, maintaining data
integrity. Write cycle timing specifications must be
observed concurrently.
SOFTWARE DATA PROTECTION
Compare
Ok?
Yes
FT28C512
Ready
No
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to imple-
ment DATA Polling. This can be especially helpful in an
array comprised of multiple
FT28C512/513
memories
that is frequently updated. Toggle Bit Polling can also
The
FT28C512/513
offers a software controlled data
protection feature. The
FT28C512/513
is shipped from
Force
with the software data protection NOT
ENABLED; that is, the device will be in the standard
operating mode. In this mode data should be protected
during power-up/-down operations through the use of
external circuits. The host would then have open read
and write access of the device once V
CC
was stable.
Rev A
5/25
2011
MCU
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