AGL125V5-FVQG100 datasheet, PDF

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AGL125V5-FVQG100: DescriptionField Programmable Gate Array, 3072 CLBs, 125000 Gates, 108MHz, CMOS, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100; CategoryProgrammable logic devices Programmable logic; File Size5MB，178 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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AGL125V5-FVQG100 Overview

Field Programmable Gate Array, 3072 CLBs, 125000 Gates, 108MHz, CMOS, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100

AGL125V5-FVQG100 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microsemi
package instruction	TFQFP,
Reach Compliance Code	compliant
maximum clock frequency	108 MHz
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
length	14 mm
Configurable number of logic blocks	3072
Equivalent number of gates	125000
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
organize	3072 CLBS, 125000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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Product Brief

1 – IGLOO Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

1.2 V or 1.5 V Core and I/O Voltage for Low Power

Supports Single-Voltage System Operation

5 µW Power Consumption in Flash*Freeze Mode

Low-Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power

Flash*Freeze Mode

•

Advanced I/O

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage

Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V

PCI-X

†

, and LVCMOS 2.5 V / 5.0 V Input

†

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and

M-LVDS (AGL250 and above)

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

‡

• Programmable Output Slew Rate

†

and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

†

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

High Capacity

• 15 k to 1 Million System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced

Encryption Standard (AES) Decryption (except ARM

enabled IGLOO

devices) via JTAG (IEEE 1532–

compliant)

†

• FlashLock

to Secure FPGA Contents

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

†

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit

RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except ×18)

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

ARM Processor Support in IGLOO FPGAs

• M1 IGLOO Devices—Cortex™-M1 Soft Processor

Available with or without Debug

AGL060 AGL125

60 k

512

1,536

Yes

125 k

1,024

3,072

Yes

133

AGL250

AGL600

AGL1000

M1AGL250 M1AGL600 M1AGL1000

250 k

600 k

–

6,144

13,824

24,576

108

144

Yes

143

235

300

CS196

QN132

3,5

VQ100

FG144

CS281

FG144,

FG256,

FG484

CS281

FG144,

FG256,

FG484

Table 1-1 •

IGLOO Product Family

IGLOO Devices

ARM-Enabled IGLOO Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

QFN

VQFP

FBGA

AGL015

15 k

128

384

–

AGL030

30 k

256

768

–

UC81, CS81

QN132

VQ100

QN68

CS121

CS196

QN132

VQ100 VQ100

FG144

Notes:

1. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

2. For higher densities and support of additional features, refer to the

IGLOOe Low-Power Flash FPGAs with

Flash*Freeze Technology

handbook.

3. Device/package support TBD.

4. AES is not available for ARM-enabled IGLOO devices.

5. The M1AGL250 device does not support this package.

† AGL015 and AGL030 devices do not support this feature.

March 2008

‡ Supported only by AGL015 and AGL030 devices.

1 -1

Product Brief

IGLOO Low-Power Flash FPGAs

Introduction and Overview

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip

solution, small footprint packages, reprogrammability, and an abundance of advanced features.

The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low-power mode that

consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze technology simplifies power

management through I/O and clock management with rapid recovery to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption (from 12 µW) while the

IGLOO device is completely functional in the system. This allows the IGLOO device to control system power

management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power.

Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power, single-chip

solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-market benefits at an

ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design flows and

tools.

IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock

conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and AGL030 devices have no

PLL or RAM support. IGLOO devices have up to 1 million system gates, supported with up to 144 kbits of true

dual-port SRAM and up to 300 user I/Os.

M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for

implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a

three-stage pipeline that offers a good balance between low-power consumption and speed when

implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction set, has a configurable

nested interrupt controller, and can be implemented with or without the debug block. Cortex-M1 is available

for free from Actel for use in M1 IGLOO FPGAs.

The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support AES

decryption.

Flash*Freeze Technology

The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low-power

Flash*Freeze mode. IGLOO devices do not need additional components to turn off I/Os or clocks while retaining

the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system

programmability, which enables users to quickly and easily upgrade and update their designs in the final stages

of manufacturing or in the field. The ability of IGLOO V2 devices to support a 1.2 V core voltage allows further

reduction in power consumption, thus achieving the lowest total system power.

When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to

the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-voltage

solution, and availability of small-footprint, high pin-count packages, make IGLOO devices the best fit for

portable electronics.

Flash Advantages

Low Power

Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice

for power-sensitive applications. IGLOO devices have only a very limited power-on current surge and no high-

current transition period, both of which occur on many FPGAs.

IGLOO devices also have low dynamic power consumption to further maximize power savings; power is even

further reduced by the use of a 1.2 V core voltage.

Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology,

gives the IGLOO device the lowest total system power offered by any FPGA.

Product Brief

1 -5

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