CY14MC256J
CY14MB256J
CY14ME256J
256-Kbit (32 K × 8) Serial (I
2
C) nvSRAM
256-Kbit (32 K × 8) Serial (I
2
C) nvSRAM
Features
■
■
256-Kbit nonvolatile static random access memory (nvSRAM)
❐
Internally organized as 32 K × 8
❐
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I
2
C
command (Software STORE) or HSB pin (Hardware STORE)
❐
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I
2
C command (Software RECALL)
❐
Automatic STORE on power-down with a small capacitor
(except for CY14MX256J1)
High reliability
❐
❐
❐
Industry standard configurations
❐
Operating voltages:
• CY14MC256J: V
CC
= 2.4 V to 2.6 V
• CY14MB256J: V
CC
= 2.7 V to 3.6 V
• CY14ME256J: V
CC
= 4.5 V to 5.5 V
❐
Industrial temperature
❐
8- and 16-pin small outline integrated circuit (SOIC) package
❐
Restriction of hazardous substances (RoHS) compliant
Overview
The
Cypress
CY14MC256J/CY14MB256J/CY14ME256J
combines a 256-Kbit nvSRAM
[2]
with a nonvolatile element in
each memory cell. The memory is organized as 32 K words of
8 bits each. The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down (except for CY14MX256J1). On
power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL
operations can also be initiated by the user through I
2
C
commands.
■
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85
C
■
High speed I
2
C interface
[1]
❐
Industry standard 100 kHz and 400 kHz speed
❐
Fast-mode Plus: 1 MHz speed
❐
High speed: 3.4 MHz
❐
Zero cycle delay reads and writes
Write protection
❐
Hardware protection using Write Protect (WP) pin
❐
Software block protection for one quarter, half, or entire array
I C access to special functions
❐
Nonvolatile STORE/RECALL
❐
8 byte serial number
❐
Manufacturer ID and Product ID
❐
Sleep mode
Low power consumption
❐
Average active current of 1 mA at 3.4-MHz operation
❐
Average standby mode current of 150 µA
❐
Sleep mode current of 8 µA
2
■
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
Slave Address
pins
CY14MX256J1 CY14MX256J2 CY14MX256J3
No
Yes
No
A2, A1, A0
Yes
Yes
No
A2, A1
Yes
Yes
Yes
A2, A1, A0
■
■
Logic Block Diagram
V
CC
V
CAP
Serial Number
8x8
Manufacturer ID /
Product ID
Memory Control Register
Command Register
Sleep
QuantumTrap
32 K x 8
SRAM
32 K x 8
STORE
RECALL
Power Control
Block
SDA
SCL
A2, A1, A0
WP
I C Control Logic
Slave Address
Decoder
2
Control Registers Slave
Memory Slave
Memory
Address and Data
Control
Notes
1. The I
2
C nvSRAM is a single solution which is usable for all four speed modes of operation. As a result, some I/O parameters are slightly different than those on chips
which support only one mode of operation. Refer to
AN87209
for more details.
2. Serial (I
2
C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation
Document Number: 001-65233 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 29, 2013
CY14MC256J
CY14MB256J
CY14ME256J
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
I2C Interface ...................................................................... 4
Protocol Overview ............................................................ 4
I2C Protocol – Data Transfer ....................................... 4
Data Validity ................................................................ 5
START Condition (S) ................................................... 5
STOP Condition (P) ..................................................... 5
Repeated START (Sr) ................................................. 5
Byte Format ................................................................. 5
Acknowledge / No-acknowledge ................................. 5
High Speed Mode (Hs-mode) ...................................... 6
Slave Device Address ................................................. 7
Write Protection (WP) .................................................. 9
AutoStore Operation .................................................... 9
Hardware STORE and HSB pin Operation ................. 9
Hardware RECALL (Power-Up) .................................. 9
Write Operation ......................................................... 10
Read Operation ......................................................... 10
Memory Slave Access ............................................... 10
Control Registers Slave ............................................. 14
Serial Number ................................................................. 16
Serial Number Write .................................................. 16
Serial Number Lock ................................................... 16
Serial Number Read .................................................. 16
Device ID ......................................................................... 17
Executing Commands Using Command Register ..... 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
DC Electrical Characteristics ........................................ 18
Data Retention and Endurance ..................................... 19
Thermal Resistance ........................................................ 19
AC Test Loads and Waveforms ..................................... 20
AC Test Conditions ........................................................ 20
AC Switching Characteristics ....................................... 21
Switching Waveforms .................................................... 21
nvSRAM Specifications ................................................. 22
Switching Waveforms .................................................... 22
Software Controlled STORE/RECALL Cycles .............. 23
Switching Waveforms .................................................... 23
Hardware STORE Cycle ................................................. 24
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagrams .......................................................... 26
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC Solutions ......................................................... 30
Document Number: 001-65233 Rev. *G
Page 2 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Pinouts
Figure 1. 8-pin SOIC pinout
[3]
A0
1
2
3
4
8
CY14MX256J1
7
Top View
6
not to scale
5
V
CC
WP
SCL
SDA
V
CAP
1
2
3
4
CY14MX256J2
Top View
not to scale
8
7
6
5
V
CC
WP
SCL
SDA
A1
A2
V
SS
A1
A2
VSS
Figure 2. 16-pin SOIC pinout
NC
NC
NC
NC
WP
A0
NC
VSS
1
2
3
4
5
6
7
8
16
15
CY14MX256J3
14
Top View
13
not to scale
12
11
10
9
VCC
NC
V
CAP
A2
SDA
SCL
A1
HSB
Pin Definitions
Pin Name
SCL
SDA
WP
A2–A0
[3]
HSB
I/O Type
Input
Description
Clock. Runs at speeds up to a maximum of f
SCL
.
Input/Output I/O. Input/Output of data through I
2
C interface.
Output: Is open-drain and requires an external pull-up resistor.
Input
Input
Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can be
left open if not connected.
Slave Address. Defines the slave address for I
2
C. This pin is internally pulled LOW and hence can be
left open if not connected.
Input/Output Hardware STORE Busy
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (t
HHHD
) with standard output high current and then a
weak internal pull-up resistor keeps this pin HIGH (External pull up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM
to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as no connect. It
must never be connected to ground.
No connect
No connect. This pin is not connected to the die.
Power supply Ground.
Power supply Power supply.
V
CAP
NC
V
SS
V
CC
Note
3. A0 pin is not available in CY14MX256J2.
Document Number: 001-65233 Rev. *G
Page 3 of 30
CY14MC256J
CY14MB256J
CY14ME256J
I
2
C
Interface
I
2
C bus consists of two lines – serial clock line (SCL) and serial
data line (SDA) that carry information between multiple devices
on the bus. I
2
C supports multi-master and multi-slave
configurations. The data is transmitted from the transmitter to the
receiver on the SDA line and is synchronized with the clock SCL
generated by the master.
The SCL and SDA lines are open-drain lines and are pulled up
to V
CC
using resistors. The choice of pull-up resistor on the
system depends on the bus capacitance and the intended speed
of operation. The master generates the clock and all the data
I/Os are transmitted in synchronization with this clock. The
CY14MX256J supports up to 3.4 MHz clock speed on SCL line.
Protocol Overview
This device supports only a 7-bit addressable scheme. The
master generates a START condition to initiate the
communication followed by broadcasting a slave select byte.
The slave select byte consists of a seven bit address of the slave
that the master intends to communicate with and R/W bit
indicating a read or a write operation. The selected slave
responds to this with an acknowledgement (ACK). After a slave
is selected, the remaining part of the communication takes place
between the master and the selected slave device. The other
devices on the bus ignore the signals on the SDA line till a STOP
or Repeated START condition is detected. The data transfer is
done between the master and the selected slave device through
the SDA pin synchronized with the SCL clock generated by the
master.
bit slave address and eighth bit (R/W) indicating a read (1) or a
write (0) operation. All signals are transmitted on the open-drain
SDA line and are synchronized with the clock on SCL line. Each
byte of data transmitted on the I
2
C bus is acknowledged by the
receiver by holding the SDA line LOW on the ninth clock pulse.
The request for write by the master is followed by the memory
address and data bytes on the SDA line. The writes can be
performed in burst-mode by sending multiple bytes of data. The
memory address increments automatically after receiving
/transmitting of each byte on the falling edge of 9th clock cycle.
The new address is latched just prior to sending/receiving the
acknowledgment bit. This allows the next sequential byte to be
accessed with no additional addressing. On reaching the last
memory location, the address rolls back to 0x0000 and writes
continue. The slave responds to each byte sent by the master
during a write operation with an ACK. A write sequence can be
terminated by the master generating a STOP or Repeated
START condition.
A read request is performed at the current address location
(address next to the last location accessed for read or write). The
memory slave device responds to a read request by transmitting
the data on the current address location to the master. A random
address read may also be performed by first sending a write
request with the intended address of read. The master must
abort the write immediately after the last address byte and issue
a Repeated START or STOP signal to prevent any write
operation. The following read operation starts from this address.
The master acknowledges the receipt of one byte of data by
holding the SDA pin LOW for the ninth clock pulse. The reads
can be terminated by the master sending a no-acknowledge
(NACK) signal on the SDA line after the last data byte. The
no-acknowledge signal causes the CY14MX256J to release the
SDA line and the master can then generate a STOP or a
Repeated START condition to initiate a new operation.
I
2
C Protocol – Data Transfer
Each transaction in I
2
C protocol starts with the master
generating a START condition on the bus, followed by a seven
Figure 3. System Configuration using Serial (I
2
C) nvSRAM
Vcc
R
Pmin
= (V
CC
- V
OL
max) / I
OL
R
Pmax
= t
r
/ (0.8473 * C
b
)
SDA
Microcontroller
SCL
Vcc
Vcc
A0
A1
A2
SCL
SDA
WP
A0
A1
A2
SCL
SDA
WP
A0
A1
A2
SCL
SDA
WP
CY14MX256J
#0
CY14MX256J
#1
CY14MX256J
#7
Document Number: 001-65233 Rev. *G
Page 4 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Data Validity
The data on the SDA line must be stable during the HIGH period
of the clock. The state of the data line can only change when the
clock on the SCL line is LOW for the data to be valid. There are
only two conditions under which the SDA line may change state
with SCL line held HIGH, that is, START and STOP condition.
The START and STOP conditions are generated by the master
to signal the beginning and end of a communication sequence
on the I
2
C bus.
STOP Condition (P)
A LOW to HIGH transition on the SDA line while SCL is HIGH
indicates a STOP condition. This condition indicates the end of
the ongoing transaction.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again after the STOP
condition.
START Condition (S)
A HIGH to LOW transition on the SDA line while SCL is HIGH
indicates a START condition. Every transaction in I
2
C begins
with the master generating a START condition.
Repeated START (Sr)
If an Repeated START condition is generated instead of a STOP
condition the bus continues to be busy. The ongoing transaction
on the I
2
C lines is stopped and the bus waits for the master to
send a slave ID for communication to restart.
Figure 4. START and STOP Conditions
full pagewidth
SDA
SDA
SCL
S
START Condition
P
STOP Condition
SCL
Figure 5. Data Transfer on the I
2
C Bus
handbook, full pagewidth
P
Sr
SDA
MSB
Acknowledgement
signal from slave
Acknowledgement
signal from receiver
SCL
S
or
Sr
1
2
7
8
9
ACK
1
2
3-8
9
ACK
Sr
or
P
STOP or
Repeated START
condition
START or
Repeated START
condition
Byte complete,
interrupt within slave
Clock line held LOW while
interrupts are serviced
Byte Format
Each operation in I
2
C is done using 8 bit words. The bits are sent
in MSB first format on SDA line and each byte is followed by an
ACK signal by the receiver.
An operation continues till a NACK is sent by the receiver or
STOP or Repeated START condition is generated by the master
The SDA line must remain stable when the clock (SCL) is HIGH
except for a START or STOP condition.
does not acknowledge the receipt of data and the operation is
aborted.
NACK can be generated by master during a READ operation in
following cases:
■
■
The master did not receive valid data due to noise.
The master generates a NACK to abort the READ sequence.
After a NACK is issued by the master, nvSRAM slave releases
control of the SDA pin and the master is free to generate a
Repeated START or STOP condition.
Acknowledge / No-acknowledge
After transmitting one byte of data or address, the transmitter
releases the SDA line. The receiver pulls the SDA line LOW to
acknowledge the receipt of the byte. Every byte of data
transferred on the I
2
C bus needs to be responded with an ACK
signal by the receiver to continue the operation. Failing to do so
is considered as a NACK state. NACK is the state where receiver
NACK can be generated by nvSRAM slave during a WRITE
operation in following cases:
■
nvSRAM did not receive valid data due to noise.
■
The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
Document Number: 001-65233 Rev. *G
Page 5 of 30
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