PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD44645084, 44645094, 44645184, 44645364
72M-BIT QDR
TM
II SRAM
4-WORD BURST OPERATION
Description
The
μ
PD44645084 is a 8,388,608-word by 8-bit, the
μ
PD44645094 is a 8,388,608-word by 9-bit, the
μ
PD44645184 is a
4,194,304-word by 18-bit and the
μ
PD44645364 is a 2,097,152-word by 36-bit synchronous quad data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44645084,
μ
PD44645094,
μ
PD44645184 and
μ
PD44645364 integrate unique synchronous peripheral
circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive
edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
•
1.8 ± 0.1 V power supply
•
165-pin PLASTIC BGA (15 x 17)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
Separate independent read and write data ports with concurrent transactions
•
100% bus utilization DDR READ and WRITE operation
•
Four-tick burst for reduced address frequency
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
•
User programmable impedance output
•
Fast clock cycle time : 3.7 ns (270 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)
•
Simple control logic for easy depth expansion
•
JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M18232EJ2V0DS00 (2nd edition)
Date Published February 2007 NS CP(N)
Printed in Japan
The mark <R> shows major revised points.
2006
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
μ
PD44645084, 44645094, 44645184, 44645364
Pin Configurations
165-pin PLASTIC BGA (15 x 17)
(Top View)
[
μ
PD44645084]
8M x 8-bit
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
A
NC
NC
NC
Q4
NC
Q5
V
DD
Q
NC
NC
D6
NC
NC
Q7
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NW1#
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC
NW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
A
D0 to D7
Q0 to Q7
R#
W#
NW0#, NW1#
K, K#
C, C#
CQ, CQ#
ZQ
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
DLL#
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: DLL/PLL disable
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1.
×××#
indicates active LOW signal.
2.
Refer to
Package Drawing
for the index mark.
3.
7A is expansion address for 144Mb.
Preliminary Data Sheet M18232EJ2V0DS
3
μ
PD44645084, 44645094, 44645184, 44645364
165-pin PLASTIC BGA (15 x 17)
(Top View)
[
μ
PD44645094]
8M x 9-bit
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
V
DD
Q
NC
NC
D7
NC
NC
Q8
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NC
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
A
D0 to D8
Q0 to Q8
R#
W#
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
DLL#
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: DLL/PLL disable
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1.
×××#
indicates active LOW signal.
2.
Refer to
Package Drawing
for the index mark.
3.
7A is expansion address for 144Mb.
4
Preliminary Data Sheet M18232EJ2V0DS
μ
PD44645084, 44645094, 44645184, 44645364
165-pin PLASTIC BGA (15 x 17)
(Top View)
[
μ
PD44645184]
4M x 18-bit
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DD
Q
D14
Q14
D15
D16
Q16
Q17
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
BW1#
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
D0 to D17
Q0 to Q17
R#
W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
DLL#
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: DLL/PLL disable
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1.
×××#
indicates active LOW signal.
2.
Refer to
Package Drawing
for the index mark.
3.
2A is expansion address for 144Mb.
2A of this product can also be used as NC.
Preliminary Data Sheet M18232EJ2V0DS
5
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