DATA SHEET
µ
PD464618AL, 464636AL
4M-BIT Bi-CMOS SYNCHRONOUS FAST STATIC RAM
256K-WORD BY 18-BIT / 128K-WORD BY 36-BIT
LVTTL INTERFACE/REGISTER-REGISTER/LATE WRITE
MOS INTEGRATED CIRCUIT
Description
The
µ
PD464618AL is a 262,144 words by 18 bits, and the
µ
PD464636AL is a 131,072 words by 36 bits
synchronous static RAM fabricated with advanced Bi-CMOS technology using N-channel memory cell.
This technology and unique peripheral circuits make the
µ
PD464618AL and
µ
PD464636AL a high-speed device.
The
µ
PD464618AL and
µ
PD464636AL are suitable for applications which require high-speed, low voltage, high-
density memory and wide bit configuration, such as cache and buffer memory.
These are packaged in a 119-pin plastic BGA (Ball Grid Array).
Features
•
Register to register synchronous operation
•
LVTTL 3.3 V Input / Output levels
•
Fast clock access time : 2.5 ns / 200 MHz, 3.0 ns / 166 MHz, 3.5 ns / 143 MHz
•
Asynchronous output enable control : /G
•
Single differential clock inputs
•
Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
•
Common I/O using three-state outputs
•
Internally self-timed write cycle
•
Late write with 1 dead cycle between Read-Write
•
Boundary scan (JTAG) IEEE 1149.1 compatible
•
Single +3.3 V power supply
•
Sleep mode : ZZ(Enables sleep mode, active high)
Ordering Information
Part number
Access time
2.5 ns
3.0 ns
3.5 ns
2.5 ns
3.0 ns
3.5 ns
Clock frequency
200 MHz
166 MHz
143 MHz
200 MHz
166 MHz
143 MHz
Package
119-pin plastic BGA
µ
PD464618ALS1-A5
µ
PD464618ALS1-A6
µ
PD464618ALS1-A7
µ
PD464636ALS1-A5
µ
PD464636ALS1-A6
µ
PD464636ALS1-A7
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14101EJ2V0DS00 (2nd edition)
Date Published May 1999 NS CP(K)
Printed in Japan
The mark
•
shows major revised points.
©
1999
µ
PD464618AL, 464636AL
Pin Name and Functions [
µ
PD464618ALS1]
Pin name
V
DD
V
SS
V
DD
Q
K, /K
SA0 to SA17
DQa1 to DQb9
/SS
/SW
/SBa
/SBb
/G
ZZ
NC
TMS
TDI
TCK
TDO
Description
Core Power Supply
Ground
Output Power Supply
Main Clock Input
Synchronous Address Input
Synchronous Data Input / Output
Synchronous Chip Select
Synchronous Byte Write Enable
Synchronous Byte "a" Write Enable
Synchronous Byte "b" Write Enable
Asynchronous Output Enable
Sleep Mode Enable
No Connection
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Clock Input (JTAG)
Test Data Output (JTAG)
Logically selects SRAM
Write command
Write DQa1 to DQa9
Write DQb1 to DQb9
Asynchronous input
Enables sleep mode, active high
Supplies power for output buffers
Function
Supplies power for RAM core
Data Sheet M14101EJ2V0DS00
3
µ
PD464618AL, 464636AL
Pin Name and Functions [
µ
PD464636ALS1]
Pin name
V
DD
V
SS
V
DD
Q
K, /K
SA0 to SA16
DQa1 to DQd9
/SS
/SW
/SBa
/SBb
/SBc
/SBd
/G
ZZ
NC
TMS
TDI
TCK
TDO
Description
Core Power Supply
Ground
Output Power Supply
Main Clock
Synchronous Address Input
Synchronous Data Input / Output
Synchronous Chip Select
Synchronous Byte Write Enable
Synchronous Byte "a" Write Enable
Synchronous Byte "b" Write Enable
Synchronous Byte "c" Write Enable
Synchronous Byte "d" Write Enable
Asynchronous Output Enable
Sleep Mode Enable
No Connection
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Clock Input (JTAG)
Test Data Output (JTAG)
Logically selects SRAM
Write command
Write DQa1 to DQa9
Write DQb1 to DQb9
Write DQc1 to DQc9
Write DQd1 to DQd9
Asynchronous input
Enables sleep mode, active high
Supplies power for output buffers
Function
Supplies power for RAM core
Data Sheet M14101EJ2V0DS00
5