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DPLD610-15

Description
UV PLD, 18ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24
CategoryProgrammable logic devices    Programmable logic   
File Size589KB,18 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
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DPLD610-15 Overview

UV PLD, 18ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24

DPLD610-15 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntel
Parts packaging codeDIP
package instructionDIP, DIP24,.3
Contacts24
Reach Compliance Codecompliant
Other featuresPAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
ArchitecturePAL-TYPE
maximum clock frequency50 MHz
JESD-30 codeR-GDIP-T24
JESD-609 codee0
length32.07 mm
Dedicated input times4
Number of I/O lines16
Number of entries20
Output times16
Number of product terms160
Number of terminals24
Maximum operating temperature70 °C
Minimum operating temperature
organize4 DEDICATED INPUTS, 16 I/O
Output functionMACROCELL
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programmable logic typeUV PLD
propagation delay18 ns
Certification statusNot Qualified
Maximum seat height5.72 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm

DPLD610-15 Related Products

DPLD610-15 NPLD610-15 NPLD610-10 NPLD610-25 DPLD610-10 DPLD610-25 PPLD610-10 PPLD610-15 PPLD610-25
Description UV PLD, 18ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24 OT PLD, 18ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28 OT PLD, 15ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28 OT PLD, 25ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28 UV PLD, 15ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24 UV PLD, 25ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24 OT PLD, 15ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24 OT PLD, 18ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24 OT PLD, 25ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible incompatible incompatible incompatible incompatible
Maker Intel Intel Intel Intel Intel Intel Intel Intel Intel
Parts packaging code DIP QLCC QLCC QLCC DIP DIP DIP DIP DIP
package instruction DIP, DIP24,.3 QCCJ, LDCC28,.5SQ QCCJ, LDCC28,.5SQ QCCJ, LDCC28,.5SQ DIP, DIP24,.3 DIP, DIP24,.3 DIP, DIP24,.3 DIP, DIP24,.3 DIP, DIP24,.3
Contacts 24 28 28 28 24 24 24 24 24
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant unknown unknown
Other features PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
Architecture PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE
maximum clock frequency 50 MHz 50 MHz 71.4 MHz 33.3 MHz 71.4 MHz 33.3 MHz 71.4 MHz 50 MHz 33.3 MHz
JESD-30 code R-GDIP-T24 S-PQCC-J28 S-PQCC-J28 S-PQCC-J28 R-GDIP-T24 R-GDIP-T24 R-PDIP-T24 R-PDIP-T24 R-PDIP-T24
JESD-609 code e0 e0 e0 e0 e0 e0 e0 e0 e0
length 32.07 mm 11.5062 mm 11.5062 mm 11.5062 mm 32.07 mm 32.07 mm 31.61 mm 31.61 mm 31.61 mm
Dedicated input times 4 4 4 4 4 4 4 4 4
Number of I/O lines 16 16 16 16 16 16 16 16 16
Number of entries 20 20 20 20 20 20 20 20 20
Output times 16 16 16 16 16 16 16 16 16
Number of product terms 160 160 160 160 160 160 160 160 160
Number of terminals 24 28 28 28 24 24 24 24 24
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
organize 4 DEDICATED INPUTS, 16 I/O 4 DEDICATED INPUTS, 16 I/O 4 DEDICATED INPUTS, 16 I/O 4 DEDICATED INPUTS, 16 I/O 4 DEDICATED INPUTS, 16 I/O 4 DEDICATED INPUTS, 16 I/O 4 DEDICATED INPUTS, 16 I/O 4 DEDICATED INPUTS, 16 I/O 4 DEDICATED INPUTS, 16 I/O
Output function MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
Package body material CERAMIC, GLASS-SEALED PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP QCCJ QCCJ QCCJ DIP DIP DIP DIP DIP
Encapsulate equivalent code DIP24,.3 LDCC28,.5SQ LDCC28,.5SQ LDCC28,.5SQ DIP24,.3 DIP24,.3 DIP24,.3 DIP24,.3 DIP24,.3
Package shape RECTANGULAR SQUARE SQUARE SQUARE RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE CHIP CARRIER CHIP CARRIER CHIP CARRIER IN-LINE IN-LINE IN-LINE IN-LINE IN-LINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
power supply 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
Programmable logic type UV PLD OT PLD OT PLD OT PLD UV PLD UV PLD OT PLD OT PLD OT PLD
propagation delay 18 ns 18 ns 15 ns 25 ns 15 ns 25 ns 15 ns 18 ns 25 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 5.72 mm 4.57 mm 4.57 mm 4.57 mm 5.72 mm 5.72 mm 4.32 mm 4.32 mm 4.32 mm
Maximum supply voltage 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V
Minimum supply voltage 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V
Nominal supply voltage 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount NO YES YES YES NO NO NO NO NO
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE J BEND J BEND J BEND THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
Terminal pitch 2.54 mm 1.27 mm 1.27 mm 1.27 mm 2.54 mm 2.54 mm 2.54 mm 2.54 mm 2.54 mm
Terminal location DUAL QUAD QUAD QUAD DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 7.62 mm 11.5062 mm 11.5062 mm 11.5062 mm 7.62 mm 7.62 mm 7.62 mm 7.62 mm 7.62 mm

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