HT24LC02A
CMOS 2K 2-Wire Serial EEPROM
Features
·
Operating voltage:
·
Partial page write allowed
·
8-byte Page write modes
·
Write operation with built-in timer
·
Hardware controlled write protection
·
40-year data retention
·
10
6
erase/write cycles per word
·
Industrial temperature range (-40°C to +85°C)
·
Package Types: 8SOP and SOT23-5
1.8V~5.5V for temperature
-40°C
to +85°C
·
Low power consumption
-
Operation: 5mA max.
-
Standby: 2mA max.
·
Internal organization: 256´8
·
2-wire serial interface
·
Write cycle time: 5ms max.
·
Automatic erase-before-write operation
General Description
The HT24LC02A is a 2K-bit serial read/write
non-volatile memory device using the CMOS floating
gate process. Its 2048 bits of memory are organized into
256 words and each word is 8 bits. The device is opti-
mized for use in many industrial and commercial appli-
cations where low power and low voltage operation are
essential. Up to eight HT24LC02A devices may be con-
nected to the same 2-wire bus. The HT24LC02A is
guaranteed for 1M erase/write cycles and 40-year data
retention.
Selection Table
Part No.
Capacity
V
DD
Clock
Operating
Write Speed
Rate
Current
@2.4V(ms)
(kHz)
@5.0V(mA)
400
5
5
Standby
Current
@5.0V(mA)
2
8SOP
HT24LC02A
Package
SOT23-5
Marking
2402A
HT24LC02A
256´8
1.8V~
5.5V
Block Diagram
Pin Assignment
W P
V C C
S C L
S D A
I/O
C o n tro l
L o g ic
X
D
M e m o ry
C o n tro l
L o g ic
C
E
H V P u m p
5
N C
1
8
2
7
3
6
4
5
H T 2 4 L C 0 2 A
8 S O P -A
N C
V C C
W P
S C L
S D A
1
4
2
3
T o p
V ie w
E E P R O M
A rra y
P a g e B u f
Y D E C
N C
V S S
S C L
V S S
S D A
W P
H T 2 4 L C 0 2 A
S O T 2 3 -5 -A
A d d re s s
C o u n te r
V C C
V S S
S e n s e A M P
R /W C o n tro l
Rev. 1.00
1
January 29, 2013
HT24LC02A
Pin Description
Pin Name
SDA
SCL
WP
VSS
VCC
I/O
I/O
I
I
¾
¾
Serial data inputs/output
Serial clock data input
Write protect
Negative power supply, ground
Positive power supply
Description
Absolute Maximum Ratings
Supply Voltage ..........................V
SS
-0.3V
to V
SS
+6.0V
Input Voltage .............................V
SS
-0.3V
to V
CC
+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
V
CC
I
CC1
I
CC2
V
IL
V
IH
V
OL
I
LI
I
LO
I
STB1
I
STB2
C
IN
C
OUT
Note:
Parameter
Operating Voltage
Operating Current
Operating Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Standby Current
Standby Current
Input Capacitance (See Note)
Output Capacitance (See Note)
Test Conditions
V
CC
¾
5V
5V
¾
¾
2.4V
5V
5V
5V
1.8V
¾
¾
Conditions
-40°C
to +85°C
Read at 100kHz
Write at 100kHz
¾
¾
I
OL
=2.1mA
V
IN
=0 or V
CC
V
OUT
=0 or V
CC
V
IN
=0 or V
CC
V
IN
=0 or V
CC
f=1MHz, 25°C
f=1MHz, 25°C
Min.
1.8
¾
¾
-1
0.7V
CC
¾
¾
¾
¾
¾
¾
¾
Typ.
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
T
a
=-40°C ~ +85°C
Max.
5.5
2
5
0.3V
CC
V
CC
+0.5
0.4
1
1
2
2
6
8
Unit
V
mA
mA
V
V
V
mA
mA
mA
mA
pF
pF
These parameters are periodically sampled but not 100% tested
Rev. 1.00
2
January 29, 2013
HT24LC02A
A.C. Characteristics
Symbol
f
SK
t
HIGH
t
LOW
t
r
t
f
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
AA
t
BUF
t
SP
t
WR
Parameter
Clock Frequency
Clock High Time
Clock Low Time
SDA and SCL Rise Time
SDA and SCL Fall Time
START Condition Hold Time
Note
Note
After this period the first
clock pulse is generated
Only relevant for repeated START
condition
¾
¾
¾
¾
Time in which the bus must be free
before a new transmission can start
Noise suppression time
¾
5.0V
Remark
¾
¾
¾
V
CC
=1.8V~5.0V
Min.
¾
600
1200
¾
¾
600
Max.
400
¾
¾
300
300
¾
¾
¾
¾
¾
900
¾
T
a
=-40°C ~ +85°C
V
CC
=2.5V~5.0V
Min.
¾
400
600
¾
¾
250
Max.
1000
¾
¾
300
300
¾
¾
¾
¾
¾
600
¾
kHz
ns
ns
ns
ns
ns
Unit
START Condition Setup Time
Data Input Hold Time
Data Input Setup Time
STOP Condition Setup Time
Output Valid from Clock
Bus Free Time
Input Filter Time Constant
(SDA and SCL Pins)
Write Cycle Time
600
0
150
600
¾
1200
¾
¾
250
0
100
250
¾
500
¾
¾
ns
ns
ns
ns
ns
ns
50
5
50
5
ns
ms
Write
Cycles
Endurance 25°C, Page Mode
1,000,000
Note:
These parameters are periodically sampled but not 100% tested.
For relative timing, refer to timing diagrams
Rev. 1.00
3
January 29, 2013
HT24LC02A
Functional Description
Pin Function
·
Serial clock
-
SCL
·
Acknowledge
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
·
Serial data
-
SDA
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
cycle.
D a ta a llo w e d
to c h a n g e
S D A
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
·
Write protect
-
WP
S C L
S ta rt
c o n d itio n
A d d re s s o r
a c k n o w le d g e
v a lid
N o A C K
s ta te
The HT24LC02A has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when connected to the
V
SS
. When the write protect pin is connected to Vcc,
the write protection feature is enabled and operates
as shown in the following table.
WP Pin
Status
At V
CC
At V
SS
Protect Array
Full Array (2K)
Normal Read/Write Operations
S to p
c o n d itio n
Device Addressing
The 2K EEPROM devices all require an 8-bit device ad-
dress word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
1
0
1
0
0
0
0
R /W
Memory Organization
·
HT24LC02A, 2K Serial EEPROM
Internally organized with 256 8-bit words, the 2K re-
quires an 8-bit data word address for random word ad-
dressing.
Device Operations
·
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
·
Start condition
D e v ic e A d d r e s s
Write Operations
·
Byte write
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
·
Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
Rev. 1.00
4
January 29, 2013
HT24LC02A
·
Page write
S e n d W r ite C o m m a n d
The 2K EEPROM is capable of an 8-byte page write.
A page write is initiated the same as byte write, but the
microcontroller does not send a stop condition after
the first data word is clocked in. Instead, after the
EEPROM acknowledges the receipt of the first data
word, the microcontroller can transmit up to seven
more data words. The EEPROM will respond with a
ze r o af t er eac h dat a w o r d r e c e i v e d . T h e
microcontroller must terminate the page write se-
quence with a stop condition.
The data word address lower three (2K) bits are inter-
nally incremented following the receipt of each data
word. The higher data word address bits are not incre-
mented, retaining the memory page row location (re-
fer to Page write timing).
·
Acknowledge polling
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
S e n d C o tr o ll B y te
w ith R /W = 0
(A C K = 0 )?
Y e s
N e x t O p e r a tio n
N o
Acknowledge Polling Flow
·
Current address read
To maximise bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write com-
mand have been sent. If the device is still busy imple-
menting its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
·
Write protect
The HT24LC02A has a write-protect function and pro-
gramming will then be inhibited when the WP pin is
connected to VCC. Under this mode, the HT24LC02A
is used as a serial ROM.
·
Read operations
The HT24LC02A supports three read operations,
namely, current address read, random address read
and sequential read. During read operation execution,
the read/write select bit should be set to
²1².
B y te W r ite T im in g
D e v ic e a d d r e s s
S D A
S
0
S ta rt
0
0
R /W
A C K
W o rd a d d re s s
The internal data word address counter maintains the
last address accessed during the last read or write op-
eration, incremented by one. This address stays valid
between operations as long as the chip power is main-
tained. The address roll over during read from the last
byte of the last memory page to the first byte of the first
page. The address roll over during write from the last
byte of the current page to the first byte of the same
page. Once the device address with the read/write se-
lect bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is seri-
ally clocked out. The microcontroller should respond a
No ACK (High) signal and following stop condition (re-
fer to Current read timing).
D A T A
P
A C K
A C K
S to p
P a g e W r ite T im in g
D e v ic e a d d r e s s
S D A
S
P
A C K
A C K
A C K
A C K
S to p
S ta rt
W o rd a d d re s s
D A T A n
D A T A n + 1
D A T A n + x
C u r r e n t R e a d T im in g
D e v ic e a d d r e s s
S D A
S
S ta rt
0
0
0
P
A C K
N o A C K
D A T A
S to p
Rev. 1.00
5
January 29, 2013
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