Freescale Semiconductor
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MC68331
Technical Summary
32-Bit Modular Microcontroller
1 Introduction
The MC68331, a highly-integrated 32-bit microcontroller, combines high-performance data manipula-
tion capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that
interface through a common intermodule bus (IMB). Standardization facilitates rapid development of
devices tailored for specific applications.
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The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), a general-purpose
timer (GPT), and a queued serial module (QSM).
The MCU can either synthesize an internal clock signal from an external reference or use an external
clock input directly. Operation with a 32.768-kHz reference frequency is standard. The maximum sys-
tem clock speed is 20.97 MHz. Because MCU operation is fully static, register and memory contents
are not affected by a loss of clock.
High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power
consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The
CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this
capability.
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Table 1 Ordering Information
Package Type
132-Pin PQFP
Temperature
–40 to +85
°
C
Frequency
(MHz)
16 MHz
20 MHz
–40 to +105
°
C
16 MHz
20 MHz
–40 to +125
°
C
16 MHz
20 MHz
144-Pin QFP
–40 to +85
°
C
16 MHz
20 MHz
–40 to +105
°
C
16 MHz
20 MHz
–40 to +125
°
C
16 MHz
20 MHz
Package Order
Quantity
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
Order Number
SPAKMC331CFC16
MC68331CFC16
SPAKMC331CFC20
MC68331CFC20
SPAKMC331VFC16
MC68331VFC16
SPAKMC331VFC20
MC68331VFC20
SPAKMC331MFC16
MC68331MFC16
SPAKMC331MFC20
MC68331MFC20
SPAKMC331CFV16
MC68331CFV16
SPAKMC331CFV20
MC68331CFV20
SPAKMC331VFV16
MC68331VFV16
SPAKMC331VFV20
MC68331VFV20
SPAKMC331MFV16
MC68331MFV16
SPAKMC331MFV20
MC68331MFV20
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MC68331TS/D
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TABLE OF CONTENTS
Section
1
1.1
1.2
1.3
1.4
1.5
2
2.1
2.2
2.3
2.4
2.5
Page
Introduction
1
Features ...................................................................................................................................... 4
Block Diagram ............................................................................................................................. 5
Pin Assignments ..........................................................................................................................6
Address Map ............................................................................................................................... 8
Intermodule Bus ..........................................................................................................................8
Signal Descriptions
9
Pin Characteristics ...................................................................................................................... 9
MCU Power Connections ..........................................................................................................10
MCU Driver Types ..................................................................................................................... 10
Signal Characteristics ................................................................................................................ 10
Signal Function .......................................................................................................................... 11
System Integration Module
14
Overview ...................................................................................................................................14
System Configuration and Protection ........................................................................................16
System Clock ............................................................................................................................ 21
External Bus Interface ............................................................................................................... 24
Chip Selects .............................................................................................................................. 28
General-Purpose Input/Output ..................................................................................................35
Resets .......................................................................................................................................37
Interrupts ...................................................................................................................................39
Factory Test Block ..................................................................................................................... 41
Central Processor Unit
43
Overview ...................................................................................................................................43
Programming Model .................................................................................................................. 43
Status Register .......................................................................................................................... 45
Data Types ................................................................................................................................ 45
Addressing Modes .....................................................................................................................45
Instruction Set Summary ........................................................................................................... 46
Background Debugging Mode ................................................................................................... 50
Queued Serial Module
51
Overview ...................................................................................................................................51
Pin Function ..............................................................................................................................52
QSM Registers .......................................................................................................................... 53
QSPI Submodule ....................................................................................................................... 56
SCI Submodule ......................................................................................................................... 64
General-Purpose Timer Module
70
Overview ...................................................................................................................................70
Capture/Compare Unit .............................................................................................................. 71
Pulse-Width Modulator ..............................................................................................................74
GPT Registers ........................................................................................................................... 75
Summary of Changes
82
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3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5
5.1
5.2
5.3
5.4
5.5
6
6.1
6.2
6.3
6.4
7
MC68331TS/D
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1.1 Features
• Modular Architecture
• Central Processing Unit (CPU32)
— Upward Object Code Compatible
— New Instructions for Controller Applications
— 32-Bit Architecture
— Virtual Memory Implementation
— Loop Mode of Instruction Execution
— Table Lookup and Interpolate Instruction
— Improved Exception Handling for Controller Applications
— Trace on Change of Flow
— Hardware Breakpoint Signal, Background Mode
— Fully Static Operation
• System Integration Module (SIM)
— External Bus Support
— Programmable Chip-Select Outputs
— System Protection Logic
— Watchdog Timer, Clock Monitor, and Bus Monitor
— System Protection Logic
— System Clock Based on 32.768-kHz Crystal for Low Power Operation
— Test/Debug Submodule for Factory/User Test and Development
• Queued Serial Module (QSM)
— Enhanced Serial Communication Interface (SCI), Universal Asynchronous Receiver Transmit-
ter (UART): Modulus Baud Rate, Parity
— Queued Serial Peripheral Interface (QSPI): 80-Byte RAM, Up to 16 Automatic Transfers
— Dual Function I/O Ports
— Continuous Cycling, 8 to 16 Bits per Transfer
• General-Purpose Timer (GPT)
— Two 16-Bit Free-Running Counters With One Nine-Stage Prescaler
— Three Input Capture Channels
— Four Output Compare Channels
— One Input Capture/Output Compare Channel
— One Pulse Accumulator/Event Counter Input
— Two Pulse-Width Modulation Outputs
— Optional External Clock Input
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1.2 Block Diagram
CHIP
SELECTS
CONTROL
PORT C
PWMA
PWMB
PCLK
PAI
PWMA
PWMB
PCLK
PAI
BR
BG
BGACK
CS[10:0]
FC2
FC1
FC0
CSBOOT
ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1/CS4
PC0/FC0/CS3
BGACK/CS2
BG/CS1
BR/CS0
ADDR[23:19]
GPT
PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
PORT GP
CONTROL
ADDR[23:0]
ADDR[18:0]
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RXD
PQS7/TXD
PQS6/PCS3
PQS5/PCS2
PQS4/PCS1
PQS3/PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
TXD
PCS3
PCS2
PCS1
PCS0/SS
SCK
MOSI
MISO
EBI
DATA[15:0]
DATA[15:0]
PORTQS
CONTROL
CONTROL
PORT E
IMB
SIZ1
SIZ0
DS
AS
RMC
AVEC
DSACK1
DSACK0
PE7/SIZ1
PE6/SIZ0
PE5/DS
PE4/AS
PE3/RMC
PE2/AVEC
PE1/DSACK1
PE0/DSACK0
QSM
CPU32
IRQ[7:1]
R/W
RESET
HALT
BERR
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CLKOUT
XTAL
EXTAL
MODCLK
CLOCK
BKPT
IFETCH
IPIPE
DSI
DSO
DSCLK
FREEZE
TEST
CONTROL
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
QUOT
CONTROL
TSC
CONTROL
PORT F
TSC
FREEZE/QUOT
331 BLOCK
Figure 1 MCU Block Diagram
MC68331TS/D
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