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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
ADuC841–SPECIFICATIONS
1
T(AVT = DVT
to 5.5V. V
= 2.5 V Internal Reference, MCLKIN = 16 MHz All specifications
=
to
DD
REF
A
MIN
PRELIMINARY TECHNICAL DATA
DD
= 2.7V to 3.3V or 4.5V
MAX
, unless otherwise noted.)
Parameter
ADC CHANNEL SPECIFICATIONS
DC ACCURACY
2,3
Resolution
Integral Nonlinearity
Differential Nonlinearity
Integral Nonlinearity
9
Differential Nonlinearity
9
Code Distrbution
CALIBRATED ENDPOINT ERRORS
4,5
Offset Error
Offset Error Match
Gain Error
Gain Error Match
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
6
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
7
ANALOG INPUT
Input Voltage Ranges
Leakage Current
Input Capacitance
TEMPERATURE SENSOR
8
Voltage Output at 25°C
Voltage TC
Accuracy
Accuracy
DAC CHANNEL SPECIFICATIONS
Internal Buffer Enabled
DC ACCURACY
10
Resolution
Relative Accuracy
Differential Nonlinearity
11
Offset Error
Gain Error
Gain Error Mismatch
ANALOG OUTPUTS
Voltage Range_0
Voltage Range_1
Output Impedance
I
SINK
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
V
DD
= 5 V
V
DD
= 3 V
Unit
Test Conditions/Comments
f
SAMPLE
= 147 kHz,
12
±1
±0.3
±0.9
±0.25
±1.5
+1.5/-0.9
1
±2
±1
±2
–85
12
±1
±0.3
±0.9
±0.25
±1.5
+1.5/-0.9
1
±3
±1
±3
–85
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB max
LSB typ
LSB max
LSB typ
LSB max
dB typ
f
IN
= 10 kHz Sine Wave
f
SAMPLE
= 147 kHz
71
–85
–85
–80
0 to V
REF
±1
32
650
–2.0
±3
±1.5
71
–85
–85
–80
0 to V
REF
±1
32
650
–2.0
±3
±1.5
dB typ
dB typ
dB typ
dB typ
Volts
µA max
pF typ
mV typ
mV/°C typ
°C typ
°C typ
2.5V Internal Reference
2.5V Internal Reference
1V External Reference
1V External Reference
ADC Input is a DC Voltage
Internal 2.5V V
REF
External 2.5V V
REF
DAC Load to AGND
R
L
= 10kΩ, C
L
= 100 pF
12
±3
-1
±1/2
±50
±1
±1
0.5
0 to V
REF
0 to V
DD
0.5
50
15
10
12
±3
-1
±1/2
±50
±1
±1
0.5
0 to V
REF
0 to V
DD
0.5
50
15
10
Bits
LSB typ
LSB max
LSB typ
mV max
% max
% typ
% typ
V typ
V typ
Ω
typ
µA typ
µs typ
nV sec typ
Guaranteed 12-Bit Monotonic
V
REF
Range
AV
DD
Range
VREF Range
% of Full-Scale on DAC1
DAC V
REF
= 2.5V
DAC V
REF
= V
DD
Full-Scale Settling Time to
Within 1/2 LSB of Final Value
1 LSB Change at Major Carry
–2–
REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC841
Parameter
DAC CHANNEL SPECIFICATIONS
12,13
Internal Buffer Disabled
DC ACCURACY
10
Resolution
Relative Accuracy
Differential Nonlinearity
11
Offset Error
Gain Error
Gain Error Mismatch
ANALOG OUTPUTS
Voltage Range_0
REFERENCE INPUT/OUTPUT
REFERENCE OUPUT
14
Output Voltage (V
REF
)
Accuracy
Power Supply Rejection
Reference Temperature Coefficient
Internal V
REF
Power-On Time
EXTERNAL REFERNCE INPUT
15
Voltage Range (V
REF
)
9
Input Impedance
Input Leakage
POWER SUPPLY MONITOR (PSM)
DV
DD
Trip Point Selection Range
DV
DD
Power Supply Trip Point
Accuracy
WATCH DOG TIMER (WDT)
9
Time-out Period
FLASH/EE MEMORY RELIABILITY
CHARACTERISTICS
16
Endurance
17
Data Retention
18
DIGITAL INPUTS
Input High Voltage (V
INH
)
Input Low Voltage (V
INL
)
Input Leakage Current (Port 0,1, EA)
Logic 1 Input Current
(All Digital Inputs)
Logic 0 Input Current (Port 2, 3)
Logic 1-0 Transition Current (Port 2, 3)
CRYSTAL OSCILLATOR
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
VINH, Input High Voltage
REV. PrC
2.63
4.37
Vmin
Vmax
Four Trip Points Selectable in
This Range Programmed via
TPD1–0 in PSMCON
12
±3
-1
±1/2
±10
±1
0.5
0 to V
REF
12
±3
-1
±1/2
±10
±1
0.5
0 to V
REF
Bits
LSB typ
LSB max
LSB typ
mV max
% typ
% typ
V typ
V
DD
= 5 V
V
DD
= 3 V
Unit
Test Conditions/Comments
Guaranteed 12-Bit Monotonic
V
REF
Range
VREF Range
% of Full-Scale on DAC1
DAC V
REF
= 2.5V
2.5
±2.5
47
±20
80
0.1
V
DD
20
10
2.5
±2.5
57
±20
80
0.1
V
DD
20
10
V
% max
dB typ
ppm/°C typ
ms typ
V min
V max
kΩ typ
µA max
Of V
REF
measured at the C
REF
pin
Internal Band Gap Deselected via
ADCCON1.6
±3.5
0
2000
0
2000
% max
ms min
ms max.
Nine Time-out Periods
Selectable in This Range
100,000
100
2.4
0.8
±10
±1
±10
±1
–80
–40
–700
–400
100,000
100
Cycles min
Years min
V min
V max
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
±1
V
IN
= 0 V or V
DD
V
IN
= 0 V or V
DD
V
IN
= V
DD
V
IN
= V
DD
V
IL
= 0 V
V
IL
= 2 V
V
IL
= 2 V
±1
–40
–400
0.8
3.5
0.4
2.5
–3–
V typ
V typ
ADuC841–SPECIFICATIONS
1
Parameter
XTAL1 Input Capacitance
XTAL2 Output Capacitance
MCU Clock Rate
DIGITAL OUTPUTS
Output High Voltage (V
OH
)
V
DD
=5V
18
18
16
2.4
4.0
Output Low Voltage (V
OL
)
ALE, Ports 0 and 2
Port 3
SCLOCK/SDATA
Floating State Leakage Current
Floating State Output Capacitance
START UP TIME
At Power-On
From Idle Mode
From Power-Down Mode
Wakeup with INT0 Interrupt
Wakeup with SPI/I
2
C Interrupt
Wakeup with External RESET
After External RESET in Normal Mode
After WDT Reset in Normal Mode
POWER REQUIREMENTS
19,20
Power Supply Voltages
AV
DD
/ DV
DD
- AGND
4.5
5.5
Power Supply Currents Normal Mode
D
VDD
Current
9
A
VDD
Current
9
D
VDD
Current
A
VDD
Current
Power Supply Currents Idle Mode
D
VDD
Current
9
A
VDD
Current
9
D
VDD
Current
9
A
VDD
Current
9
Power Supply Currents Power Down Mode
A
VDD
Current
D
VDD
Current
V
DD
=3V
18
18
8
2.4
2.6
PRELIMINARY TECHNICAL DATA
Units
pF typ
pF typ
MHz max
V min
V typ
V
DD
= 4.5 V to 5.5 V
I
SOURCE
= 80 µA
V
DD
= 2.7 V to 3.3 V
I
SOURCE
= 20 µA
I
SINK
= 1.6 mA
I
SINK
= 1.6 mA
I
SINK
= 4 mA
I
SINK
= 8 mA
Test Conditions
0.4
0.2
0.4
0.4
±10
±1
10
0.4
0.2
0.4
0.4
±10
±1
10
V max
V typ
Vmax
Vmax
µA max
µA typ
pF typ
Core CLK = 16MHz
500
100
150
150
150
3
3
500
100
400
400
400
3
3
ms typ
µs typ
ms typ
ms typ
ms typ
ms typ
ms typ
Controlled via WDCON SFR
2.7
3.3
V min.
V max.
V min.
V max.
AV
DD
/ DV
DD
= 3V nom.
AV
DD
/ DV
DD
= 5V nom.
12
1.4
25
21
1.4
6
1.4
n/a
n/a
n/a
mA typ
mA max
mA max
mA typ
mA max
Core CLK=8 MHz
Core CLK=16 MHz
5
0.11
11
10
0.11
2.5
0.11
n/a
n/a
n/a
mA typ
mA typ
mA max
mA typ
mA typ
Core CLK=8 MHz
Core CLK=16 MHz
For any Core CLK
3
35
25
120
2.5
15
12
120
uA typ
uA max
uA typ
uA typ
TIMECON.1=0
TIMECON.1=1
AVDD = DVDD = 5V
50
1.5
150
uA typ
mA typ
uA typ
Typical Additional Power Supply Currents
PSM Peripheral
ADC
DAC
–4–
REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC841
NOTES
1
Temperature Range -40ºC to +85ºC.
2
ADC Linearity is guaranteed during normal MicroConverter Core operation.
3
ADC LSB Size = Vref / 2^12 i.e for Internal Vref=2.5V, 1LSB = 610uV and for External Vref =1V, 1LSB = 244uV.
4
Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration.
5
Based on external ADC system components the user may need to execute a system calibration to remove additional external channel errors
and achieve these specifications.
6
SNR calculation includes distortion and noise components.
7
Channel to Channel Crosstalk is measured on adjacent channels.
8
The Temperature Monitor will give a measure of the die temperature directly, air temperature can be inferred from this result.
9
These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release.
10
DAC linearity is calculated using :
reduced code range of 48 to 4095, 0 to Vref range.
reduced code range of 48 to 3945, 0 to V
DD
range.
DAC Output Load = 10K Ohms and 100 pF.
11
DAC Differential NonLinearity specified on 0 to Vref and 0 to Vdd ranges
12
DAC specification for output impedance in the unbuffered case depends on DAC code
13
DAC specifications for Isink, voltage output settling time and digital-to-analog glitch engergy depend on external buffer implementation in unbuffered mode.
14
Measured with Vref and Cref pins decoupled with 0.1µF capacitors to graound. Power-up time for the Internal Reference will be determined
by the value of the decoupling capacitor chosen for both the Vref and Cref pins.
15
When using an External Reference device, the internal bandgap reference input can be bypassed by setting the ADCCON1.6 bit. In this
mode the Vref and Cref pins need to be shorted together for correct operation.
16
Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
17
Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at -40ºC, +25ºC, and +85ºC, typical endurance at
25ºC is 700 Kcycles.
18
Retention lifetime equivalent at junction temperature (Tj) = 55ºC as per JEDEC Std. 22 method A117. Retention lifetime based on an
activation energy of 0.6eV will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this
data sheet.
19
Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Executing internal software loop.
Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Execution suspended in idle mode.
Power-Down Mode:Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O pins and Port 1 are open circuit, OSC off, TIC off.
20
D
VDD
power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
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