Quad 12-Bit Serial
Voltage Output DAC
DAC8420
FEATURES
Guaranteed monotonic over temperature
Excellent matching between DACs
Unipolar or bipolar operation
Buffered voltage outputs
High speed serial digital interface
Reset-to-zero scale or midscale
Wide supply range, +5 V only to ±15 V
Low power consumption (35 mW maximum)
Available in 16-Lead PDIP, SOIC, and CERDIP packages
FUNCTIONAL BLOCK DIAGRAM
VREFHI
5
VDD
1
DAC8420
SDI
10
REG
A
12
CS
12
CLK
11
SHIFT
REGISTER
REG
B
DAC B
6
DAC A
7
VOUTA
VOUTB
APPLICATIONS
Software controlled calibration
Servo controls
Process control and automation
ATE
NC
13
4
REG
C
DAC C
3
VOUTC
LD
14
DECODE
2
REG
D
DAC D
2
VOUTD
9
16
15
4
8
GND
CLSEL CLR
VREFLO
VSS
Figure 1.
GENERAL DESCRIPTION
The DAC8420 is a quad, 12-bit voltage-output DAC with serial
digital interface in a 16-lead package. Utilizing BiCMOS tech-
nology, this monolithic device features unusually high circuit
density and low power consumption. The simple, easy-to-use
serial digital input and fully buffered analog voltage outputs
require no external components to achieve a specified per-
formance.
The 3-wire serial digital input is easily interfaced to micro-
processors running at 10 MHz with minimal additional
circuitry. Each DAC is addressed individually by a 16-bit
serial word consisting of a 12-bit data word and an address
header. The user-programmable reset control CLR forces all
four DAC outputs to either zero scale or midscale,
asynchronously overriding the current DAC register values. The
output voltage range, determined by the inputs VREFHI and
VREFLO, is set by the user for positive or negative unipolar or
bipolar signal swings within the supplies, allowing considerable
design flexibility.
The DAC8420 is available in 16-lead PDIP, SOIC, and CERDIP
packages. Operation is specified with supplies ranging from
+5 V only to ±15 V, with references of +2.5 V to ±10 V, respec-
tively. Power dissipation when operating from ±15 V supplies is
less than 255 mW (maximum) and only 35 mW (maximum)
with a +5 V supply.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
00275-001
DAC8420
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 14
Introduction ................................................................................ 14
Digital Interface Operation ....................................................... 14
Correct Operation of CS and CLK........................................... 14
Using CLR and CLSEL .............................................................. 14
Programming the Analog Outputs .......................................... 14
VREFHI Input Requirements................................................... 16
Power-Up Sequence ................................................................... 16
Applications..................................................................................... 17
Power Supply Bypassing and Grounding................................ 17
Analog Outputs .......................................................................... 17
Reference Configuration ........................................................... 18
Isolated Digital Interface ........................................................... 19
Dual Window Comparator ....................................................... 20
MC68HC11 Microcontroller Interfacing................................ 20
DAC8420 to M68HC11 Interface Assembly Program .......... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 23
REVISION HISTORY
5/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Endnote 3 ...................................................................... 4
Changes to Table 3............................................................................ 6
Changes to Table 4............................................................................ 2
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 23
9/03—Rev. 0 to Rev. A
Changes to General Description .................................................... 1
Deleted Wafer Test Limits table ...................................................... 4
Deleted Dice Characteristics........................................................... 4
Updated Ordering Guide................................................................. 4
Added Power-Up Sequence section ............................................. 12
Updated Outline Dimensions ....................................................... 17
Rev. B | Page 2 of 24
DAC8420
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
1
@ V
DD
= +5.0 V ± 5%, V
SS
= 0 V, V
VREFHI
= +2.5 V, V
VREFLD
= 0 V, and V
SS
= −5.0 V ± 5%, V
VREFLO
= −2.5 V, −40°C ≤ T
A
≤ +85°C unless
otherwise noted.
2
Table 1.
Parameter
STATIC ACCURACY
Integral Linearity E Grade
Integral Linearity E Grade
Integral Linearity F Grade
Integral Linearity F Grade
Differential Linearity
Zero-Scale Error
Full-Scale Error
Zero-Scale Error
Full-Scale Error
Zero-Scale Temperature Coefficient
Full-Scale Temperature Coefficient
MATCHING PERFORMANCE
Linearity Matching
REFERENCE
Positive Reference Input Range
5
Negative Reference Input Range
5
Negative Reference Input Range
Reference High Input Current
Reference Low Input Current
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Input Capacitance
4
LOGIC TIMING CHARACTERISTICS
4, 7
Data Setup Time
Data Hold
Clock Pulse Width High
Clock Pulse Width Low
Select Time
Deselect Delay
Load Disable Time
Load Delay
Load Pulse Width
Clear Pulse Width
Symbol
INL
INL
INL
INL
DNL
ZSE
FSE
ZSE
FSE
TC
ZSE
TC
FSE
Condition
Min
Typ
±¼
±½
±¾
±1
±¼
Max
±1
±3
±2
±4
±1
±4
±4
±8
±8
Unit
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
V
DD
− 2.5
V
VREFHI
− 2.5
V
VREFHI
− 2.5
+0.75
V
V
V
mA
mA
mA
μs
V/μs
V
V
μA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
SS
= 0 V
3
V
SS
= 0 V
3
Monotonic over temperature
R
L
= 2 kΩ, V
SS
= −5 V
R
L
= 2 kΩ, V
SS
= −5 V
R
L
= 2 kΩ, V
SS
= 0 V
3
R
L
= 2 kΩ, V
SS
= 0 V
3
R
L
= 2 kΩ, V
SS
= −5 V
4
R
L
= 2 kΩ, V
SS
= −5 V
4
±10
±10
±1
V
VREFHI
V
VREFLO
V
VREFLO
I
VREFHI
I
VREFLO
I
OUT
t
S
SR
V
INH
V
INL
I
IN
C
IN
t
DS
t
DH
t
CH
t
CL
t
CSS
t
CSH
t
LD1
t
LD2
t
LDW
t
CLRW
V
SS
= 0 V
5
Code 0x000, Code 0x555
Code 0x000, Code 0x555, V
SS
= −5 V
V
SS
= −5 V
To 0.01%
6
10% to 90%
6
V
VREFLO
+ 2.5
V
SS
0
−0.75
−1.0
−1.25
±0.25
−0.6
+1.25
8
1.5
2.4
0.8
10
13
25
55
90
120
90
5
130
35
80
150
Rev. B | Page 3 of 24
DAC8420
Parameter
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
1
2
Symbol
PSRR
I
DD
I
SS
P
DISS
Condition
Min
Typ
0.002
4
−3
20
Max
0.01
7
35
Unit
%/%
mA
mA
mW
−6
V
SS
= 0 V
Typical values indicate performance measured at 25°C.
All supplies can be varied ±5% and operation is guaranteed. Device is tested with V
DD
= 4.75 V.
3
For single-supply operation (V
VREFLO
= 0 V, V
SS
= 0 V), due to internal offset errors INL and DNL are measured beginning at Code 0x005.
4
Guaranteed, but not tested.
5
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
6
V
OUT
swing between +2.5 V and −2.5 V with V
DD
= 5.0 V.
7
All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Rev. B | Page 4 of 24
DAC8420
@ V
DD
= +15.0 V ± 5%, V
SS
= −15.0 V ± 5%, V
VREFHI
= +10.0 V, V
VREFLO
= −10.0 V, −40°C ≤ T
A
≤ +85°C unless otherwise noted.
1, 2
Table 2.
Parameter
STATIC ACCURACY
Integral Linearity E Grade
Integral Linearity F Grade
Differential Linearity
Zero-Scale Error
Full-Scale Error
Zero-Scale Temperature Coefficient
Full-Scale Temperature Coefficient
MATCHING PERFORMANCE
Linearity Matching
REFERENCE
Positive Reference Input Range
4
Negative Reference Input Range
4
Reference High Input Current
Reference Low Input Current
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
DYNAMIC PERFORMANCE
Analog Crosstalk
3
Digital Feedthrough
3
Large Signal Bandwidth
Glitch Impulse
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Input Capacitance
3
LOGIC TIMING CHARACTERISTICS
3, 6
Data Setup Time
Data Hold
Clock Pulse Width High
Clock Pulse Width Low
Select Time
Deselect Delay
Load Disable Time
Load Delay
Load Pulse Width
Clear Pulse Width
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
1
2
Symbol
INL
INL
DNL
ZSE
FSE
TC
ZSE
TC
FSE
Condition
Min
Typ
±¼
±½
±¼
Max
±½
±1
±1
±2
±2
Unit
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
Monotonic over temperature
R
L
= 2 kΩ
R
L
= 2 kΩ
R
L
= 2 kΩ
3
R
L
= 2 kΩ
3
±4
±4
±1
V
VREFHI
V
VREFLO
I
VREFHI
I
VREFLO
I
OUT
t
S
SR
Code 0x000, Code 0x555
Code 0x000, Code 0x555
V
VREFLO
+ 2.5
−10
−2.0
−3.5
−5
±1.0
−2.0
V
DD
− 2.5
V
VREFHI
− 2.5
+2.0
V
V
mA
mA
mA
μs
V/μs
dB
dB
kHz
μV-s
V
V
μA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
+5
13
2
>64
>72
90
6
To 0.01%
10% to 90%
5
5
3 dB, V
VREFHI
= 5 V + 10 V p-p, V
VREFLO
= −10 V
3
Code Transition = 0x7FF to 0x800
3
V
INH
V
INL
I
IN
C
IN
t
DS
t
DH
t
CH
t
CL
t
CSS
t
CSH
t
LD1
t
LD2
t
LDW
t
CLRW
PSRR
I
DD
I
SS
P
DISS
2.4
0.8
10
13
25
20
30
50
55
15
40
15
45
70
0.002
6
−5
0.01
9
255
−8
%/%
mA
mA
mW
Typical values indicate performance measured at 25°C.
All supplies can be varied ±5% and operation is guaranteed.
3
Guaranteed, but not tested.
4
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
5
V
OUT
swing between +10 V and −10 V.
6
All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Rev. B | Page 5 of 24
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