Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
FEATURES
General
•
Low power consumption
•
3.0 V power supply
•
System clock of 256f
s
, 384f
s
and 512f
s
•
Supports sampling frequencies from 8 to 55 kHz
•
Non-inverting ADC plus integrated high-pass filter to
cancel DC offset
•
ADC supports 2 V (RMS) input signals
•
Overload detector for easy record level control
•
Separate power control for ADC and DAC
•
Integrated digital interpolation filter plus non-inverting
DAC
•
Functions controllable either via L3 microcontroller
interface or via static pins
•
UDA1344TS is pin and function compatible with
UDA1340M
•
Small package size (SSOP28)
•
Easy application.
Multiple format input interface
•
I
2
S-bus, MSB-justified or LSB-justified
16, 18 and 20 bits format compatible
•
Three combined data formats with MSB-justified output
and LSB-justified 16, 18 and 20 bits input
•
1f
s
input and output format data rate.
DAC digital sound processing
The sound processing features of the UDA1344TS can be
used in the L3 mode only:
•
Digital tone control, bass boost and treble
•
Digital dB-linear volume control (low microcontroller
load) via L3 microcontroller
•
Digital de-emphasis for 32, 44.1 and 48 kHz
•
Soft mute.
ORDERING INFORMATION
TYPE
NUMBER
UDA1344TS
PACKAGE
NAME
SSOP28
DESCRIPTION
Advanced audio configuration
UDA1344TS
•
Stereo single-ended input configuration
•
Stereo line output (under microcontroller volume
control), no post filter required
•
High linearity, dynamic range and low distortion.
GENERAL DESCRIPTION
The UDA1344TS is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. The low power consumption and
low voltage requirements make the device eminently
suitable for use in low-voltage low-power portable digital
audio equipment which incorporates recording and
playback functions.
The UDA1344TS supports the I
2
S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB-justified
data format with word lengths of 16, 18 and 20 bits. The
UDA1344TS also supports three combined data formats
with MSB-justified data output and LSB-justified
16, 18 and 20 bits data input.
The UDA1344TS can be controlled either via static pins or
via the L3 interface. In the L3 mode the UDA1344TS has
special Digital Sound Processing (DSP) features in
playback mode such as de-emphasis, volume control,
bass boost, treble and soft mute.
VERSION
SOT341-1
plastic shrink small outline package; 28 leads; body width 5.3 mm
2000 Feb 04
2
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
QUICK REFERENCE DATA
SYMBOL
Supplies
V
DDA(ADC)
V
DDA(DAC)
V
DDO
V
DDD
I
DDA(ADC)
I
DDA(DAC)
I
DDO
I
DDD
ADC analog supply voltage
DAC analog supply voltage
operational amplifier supply voltage
digital supply voltage
ADC analog supply current
DAC analog supply current
operational amplifier supply current
digital supply current
operating
ADC power-down
operating
DAC power-down
operating
DAC power-down
operating
DAC power-down
ADC power-down
T
amb
V
i(rms)
(THD + N)/S
S/N
α
cs
V
o(rms)
(THD + N)/S
S/N
α
cs
P
ADDA
P
DA
P
AD
P
PD
Notes
ambient temperature
Analog-to-digital converter
input voltage (RMS value)
total harmonic distortion-plus-noise to
signal ratio
signal-to-noise ratio
channel separation
notes 1 and 2
at 0 dB
at
−60
dB; A-weighted
V
i
= 0 V; A-weighted
−
−
−
−
−
notes 3 and 4
at 0 dB
at
−60
dB; A-weighted
code = 0; A-weighted
−
−
−
−
−
−
−
−
−
1.0
2.7
2.7
2.7
2.7
−
−
−
−
−
−
−
−
−
−40
PARAMETER
CONDITIONS
MIN.
UDA1344TS
TYP.
MAX.
UNIT
3.0
3.0
3.0
3.0
9.0
3.5
4.0
25
4.0
250
6.0
2.5
3.5
−
3.6
3.6
3.6
3.6
11.0
5.0
6.0
75
6.0
350
9.0
4.0
5.0
+85
−
−80
−30
−
−
−
−85
−
−
−
−
−
−
−
V
V
V
V
mA
mA
mA
µA
mA
µA
mA
mA
mA
°C
V
dB
dB
dB
dB
−85
−35
95
100
Digital-to-analog converter
output voltage (RMS value)
total harmonic distortion-plus-noise to
signal ratio
signal-to-noise ratio
channel separation
900
−90
−37
100
100
mV
dB
dB
dB
dB
Power performance
power consumption in record and
playback mode
power consumption in playback mode
power consumption in record mode
power consumption in power-down mode
69
42
37.5
17
mW
mW
mW
mW
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately
1 mA by using a series resistor.
2. The input voltage to the ADC is inversely proportional to the supply voltage.
3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M.
4. The output of the DAC scales proportionally with the supply voltage.
2000 Feb 04
3
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
PINNING
SYMBOL
V
SSA(ADC)
V
DDA(ADC)
VINL
V
ref(A)
VINR
V
ADCN
V
ADCP
MC1
MP1
V
DDD
V
SSD
SYSCLK
MP2
MP3
MP4
BCK
WS
DATAO
DATAI
MP5
MC2
V
SSA(DAC)
V
DDA(DAC)
VOUTR
V
DDO
VOUTL
V
SSO
V
ref(D)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DESCRIPTION
ADC analog ground
ADC analog supply voltage
ADC input left
ADC reference voltage
ADC input right
ADC negative reference voltage
ADC positive reference voltage
mode control 1 input (pull-down)
multi purpose pin 1 output
digital supply voltage
digital ground
system clock input:
256f
s
, 384f
s
or 512f
s
multi purpose pin 2 input
multi purpose pin 3 input
multi purpose pin 4 input
bit clock input
word select input
data output
data input
multi purpose pin 5 output
(pull-down)
mode control 2 input (pull-down)
DAC analog ground
DAC analog supply voltage
DAC output right
operational amplifier supply voltage
DAC output left
operational amplifier ground
DAC reference voltage
handbook, halfpage
UDA1344TS
VSSA(ADC) 1
VDDA(ADC) 2
VINL 3
Vref(A) 4
VINR 5
VADCN 6
VADCP 7
MC1 8
MP1 9
VDDD 10
VSSD 11
SYSCLK 12
MP2 13
MP3 14
MGL442
28 Vref(D)
27 VSSO
26 VOUTL
25 VDDO
24 VOUTR
23 VDDA(DAC)
UDA1344TS
22 VSSA(DAC)
21 MC2
20 MP5
19 DATAI
18 DATAO
17 WS
16 BCK
15 MP4
Fig.2 Pin configuration.
2000 Feb 04
5