SPI
®
-/I
2
C
®
-Compatible, 10-Bit Digital
Temperature Sensor and 8-Channel ADC
ADT7411
FEATURES
10-bit temperature-to-digital converter
10-bit 8-channel ADC
DC input bandwidth
Input range: 0 V to 2.25 V and 0 V to V
DD
Temperature range: −40°C to +120°C
Temperature sensor accuracy of ±0.5°C
Supply range: 2.7 V to 5.5 V
Power-down current : <10 μA
Internal 2.25 V
REF
option
Double-buffered input logic
I
2
C, SPI, QSPI™, MICROWIRE™, and DSP compatible
4-wire serial interface
SMBus packet error checking (PEC) compatible
16-lead QSOP
PIN CONFIGURATION
AIN6
1
AIN5
2
NC
3
CS
4
GND
5
V
DD 6
D+/AIN1
7
D–/AIN2
8
16
AIN7
15
AIN8
ADT7411
TOP VIEW
(Not to Scale)
14
AIN4
13
SCL/SCLK
12
SDA/DIN
11
DOUT/ADD
10
INT/INT
02882-005
9
AIN3
NC = NO CONNECT
Figure 1.
APPLICATIONS
Portable battery-powered instruments
PCs
Smart battery chargers
Telecommunications systems electronic test equipment
Domestic appliances
Process controls
GENERAL DESCRIPTION
The ADT7411
1
combines a 10-bit temperature-to-digital
converter and a 10-bit 8-channel ADC in a 16-lead QSOP. This
includes a band gap temperature sensor and a 10-bit ADC to
monitor and digitize the temperature reading to a resolution of
0.25°C. The ADT7411 operates from a single 2.7 V to 5.5 V
supply. The input voltage on the ADC channels has a range of
0 V to 2.25 V and the input bandwidth is dc. The reference for
the ADC channels is derived internally. The ADT7411 provides
two serial interface options: a 4-wire serial interface compatible
with SPI, QSPI, MICROWIRE, and DSP interface standards,
and a 2-wire SMBus/I
2
C interface. It features a standby mode
that is controlled via the serial interface.
The ADT7411’s wide supply voltage range, low supply current,
and SPI-/I
2
C-compatible interface make it ideal for a variety of
applications, including PCs, office equipment, and domestic
appliances.
1
Protected by U.S. Patent Numbers: 6,169,442; 5,867,012; 5,764174.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADT7411
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Functional Block Diagram .............................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Functional Descriptions.......................... 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 13
Power-Up Calibration................................................................ 13
Conversion Speed....................................................................... 13
Functional Description.................................................................. 14
Analog Inputs ............................................................................. 14
Functional Description—Measurement.................................. 15
ADT7411 Registers .................................................................... 19
Serial Interface ............................................................................ 29
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
12/06–Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Features.......................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 7
Changes to Theory of Operation Section.................................... 13
Changes to Figure 20...................................................................... 14
Changes to Table 7.......................................................................... 20
Changes to Table 16 Title............................................................... 22
Changes to Internal T
HIGH
Limit Register (Read/Write)
[Address = 25h] Section ................................................................ 25
Changes to Internal T
LOW
Limit Register (Read/Write)
[Address = 26h] Section ................................................................ 26
Changes to External T
HIGH
/AIN1 V
HIGH
Limit Register
(Read/Write) [Address = 27h] Section ........................................ 26
Changes to External T
LOW
/AIN1 V
LOW
Limit Register
(Read/Write) [Address = 28h] Section ........................................ 26
Changes to Serial Interface Selection Section............................. 29
Changes to SPI Serial Interface Section....................................... 30
Changes to Read Operation Section ............................................ 32
Changes to Ordering Guide .......................................................... 35
3/04–Rev. 0 to Rev. A
Format Updated..................................................................Universal
Change to Equation........................................................................ 17
8/03–Revision 0: Initial Version
Rev. B | Page 2 of 36
ADT7411
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Temperature ranges are −40°C to +120°C.
Table 1.
Parameter
1
ADC DC ACCURACY
Resolution
Total Unadjusted Error (TUE)
Offset Error
Gain Error
ADC BANDWIDTH
ANALOG INPUTS
Input Voltage Range
DC Leakage Current
Input Capacitance
Input Resistance
THERMAL CHARACTERISTICS
Internal Temperature Sensor
Accuracy @ V
DD
= 3.3 V ± 10%
Min
Typ
Max
10
3
2
±0.5
±2
DC
2.25
V
DD
±1
20
Unit
Bits
% of FSR
% of FSR
% of FSR
% of FSR
Hz
V
V
μA
pF
MΩ
Conditions/Comments
Maximum V
DD
= 5 V.
V
DD
= 2.7 V to 5.5 V.
V
DD
= 3.3 V (±10%).
2
0
0
5
10
AIN1 to AIN8. C4 = 0 in Control Configuration 3.
AIN1 to AIN8. C4 = 1 in Control Configuration 3.
Internal reference used. Averaging on.
±1.5
±3
±5
±3
±5
10
°C
°C
°C
°C
°C
Bits
°C
°C
°C
°C
°C
°C
Bits
μA
μA
T
A
= 85°C.
T
A
= 0°C to 85°C.
T
A
= −40°C to +120°C.
T
A
= 0°C to 85°C.
T
A
= −40°C to +120°C.
Equivalent to 0.25°C.
Drift over 10 years if part is operated at 55°C.
External transistor = 2N3906.
T
A
= 85°C.
T
A
= 0°C to 85°C.
T
A
= −40°C to +120°C.
T
A
= 0°C to 85°C.
T
A
= −40°C to +120°C.
Equivalent to 0.25°C.
High level.
Low level.
Single-channel mode.
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
Accuracy @ V
DD
= 5 V ± 5%
Resolution
Long-Term Drift
External Temperature Sensor
Accuracy @ V
DD
= 3.3 V ± 10%
±0.5
±2
±2
±3
0.25
Accuracy @ V
DD
= 5 V ± 5%
Resolution
Output Source Current
CONVERSION TIMES
Slow ADC
V
DD
/AIN
Internal Temperature
External Temperature
Fast ADC
V
DD
/AIN
Internal Temperature
External Temperature
±2
±3
180
11
±1.5
±3
±5
±3
±5
10
11.4
712
11.4
712
24.22
1.51
712
44.5
2.14
134
14.25
890
ms
μs
ms
μs
ms
ms
μs
μs
ms
μs
ms
μs
Rev. B | Page 3 of 36
ADT7411
Parameter
1
ROUND ROBIN UPDATE RATE
2
Slow ADC @ 25°C
Averaging On
Averaging Off
Averaging On
Averaging Off
Fast ADC @ 25°C
Averaging On
Averaging Off
Averaging On
Averaging Off
ON-CHIP REFERENCE
3
Reference Voltage
Temperature Coefficient
DIGITAL INPUTS
1, 3
Input Current
V
IL
, Input Low Voltage
V
IH
, Input High Voltage
Pin Capacitance
SCL, SDA Glitch Rejection
DIGITAL OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Output High Current, I
OH
Output Capacitance, C
OUT
INT/INT Output Saturation Voltage
I
2
C TIMING CHARACTERISTICS
4, 5
Serial Clock Period, t
1
Data In Setup Time to SCL High, t
2
Data Out Stable after SCL Low, t
3
SDA Low Setup Time to SCL Low
(Start Condition), t
4
SDA High Hold Time after SCL High
(Stop Condition), t
5
SDA and SCL Fall Time, t
6
SDA and SCL Rise Time, t
7
SPI TIMING CHARACTERISTICS
1, 3, 7
CS to SCLK Setup Time, t
1
SCLK High Pulse Width, t
2
SCLK Low Pulse Width, t
3
Data Access Time after SCLK Falling Edge, t
47
Data Setup Time Prior to SCLK Rising Edge, t
5
Data Hold Time after SCLK Rising Edge, t
6
CS to SCLK Hold Time, t
7
CS to DOUT High Impedance, t
8
Min
Typ
Max
Unit
Conditions/Comments
Time to complete one measurement cycle
through all channels.
AIN1 and AIN2 are selected on Pin 7 and Pin 8.
AIN1 and AIN2 are selected on Pin 7 and Pin 8.
D+ and D– are selected on Pin 7 and Pin 8.
D+ and D− are selected on Pin 7 and Pin 8.
AIN1 and AIN2 are selected on Pin 7 and Pin 8.
AIN1 and AIN2 are selected on Pin 7 and Pin 8.
D+ and D− are selected on Pin 7 and Pin 8.
D+ and D− are selected on Pin 7 and Pin 8.
125.4
17.1
140.36
12.11
9.26
578.96
24.62
3.25
2.2662
2.28
80
2.2938
ms
ms
ms
ms
ms
μs
ms
ms
V
ppm/°C
μA
V
V
pF
ns
±1
0.8
1.89
3
10
50
V
IN
= 0 V to V
DD
.
All digital inputs.
Input filtering suppresses noise spikes of less
than 50 ns.
I
SOURCE
= I
SINK
= 200 μA.
I
OL
= 3 mA.
V
OH
= 5 V.
I
OUT
= 4 mA.
Fast-mode I
2
C. See Figure 2.
See Figure 2.
See Figure 2.
See Figure 2.
See Figure 2.
See Figure 2.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
2.4
0.4
1
50
0.8
2.5
50
0
50
50
300
300
6
0
50
50
35
20
0
0
40
V
V
mA
pF
V
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. B | Page 4 of 36
ADT7411
Parameter
1
POWER REQUIREMENTS
V
DD
V
DD
Settling Time
I
DD
(Normal Mode)
8
I
DD
(Power-Down Mode)
Power Dissipation
Min
2.7
Typ
Max
5.5
50
3
3
10
10
10
33
Unit
V
ms
mA
mA
μA
μA
mW
μW
Conditions/Comments
2.2
V
DD
settles to within 10% of its final voltage level.
V
DD
= 3.3 V, V
IH
= V
DD
and V
IL
= GND.
V
DD
= 5 V, V
IH
= V
DD
and V
IL
= GND.
V
DD
= 3.3 V, V
IH
= V
DD
and V
IL
= GND.
V
DD
= 5 V, V
IH
= V
DD
and V
IL
= GND.
V
DD
= 3.3 V. Using normal mode.
V
DD
= 3.3 V. Using shutdown mode.
1
2
See the Terminology section.
Round robin is the continuous sequential measurement of the following channels: V
DD
, internal temperature, external temperature (AIN1, AIN2), AIN3, AIN4, AIN5,
AIN6, AIN7, and AIN8.
3
Guaranteed by design and characterization, not production tested.
4
The SDA and SCL timing is measured with the input filters turned on so as to meet the fast-mode I
2
C specification. Switching off the input filters improves the transfer
rate but has a negative effect on the EMC behavior of the part.
5
Guaranteed by design. Not tested in production.
6
The interface is also capable of handling the I
2
C standard mode rise time specification of 1000 ns.
7
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
), and timed from a voltage level of 1.6 V.
8
I
DD
specification is valid for full-scale analog input voltages. Interface inactive. ADC active. Load currents excluded.
t
1
SCL
t
4
SDA
DATA IN
t
2
t
5
t
3
SDA
DATA OUT
t
6
t
7
Figure 2. I C Bus Timing Diagram
2
CS
t
1
SCLK
t
2
02882-002
t
7
t
3
DIN
D7
D6
D5
D4
D3
t
5
D2
t
6
D1
D0
X
X
X
X
X
X
X
X
DOUT
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3. SPI Bus Timing Diagram
200µA
I
OL
TO
OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
02882-004
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
Rev. B | Page 5 of 36
02882-003
t
4
t
8
FPGA/CPLD
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