Intel
®
LXT385 Octal E1 Short-Haul PCM
Transceiver with Jitter Attenuation (JA)
Datasheet
Product Features
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OctalE1 Pulse-Code Modulation (PCM)
Transceiver with Jitter Attenuation for use
in 2.048 Mbps (E1) applications
8 fully-independent receiver/transmitters
Support for E1 standards:
— Exceeds ETSI ETS 300 166
Meets ETS 300 233Low-power single-rail
3.3-V CMOS power supply, with 5-V
tolerant I/Os
Jitter attenuation
— Crystal-less
— Digital clock recovery PLL
— Referenced to 2.048-MHz clock.
Normal operation requires only MCLK.
Does not require a reference clock
frequency higher than the line
frequency.
— Can be switched between receive and
transmit path
— Meets ETSI CTR12/13, ITU G.736,
G.742, and G.823
— Optimized for Synchronous Digital
Hierarchy (SDH) applications, meets
ITU G.783 mapping jitter standard
— Constant throughput delay
Differential receiver architecture
— High margin for noise interference
— Operates at >12 dB of cable attenuation
Intel
®
Hitless Protection Switching
— Eliminates mechanical relays for
redundancy 1+1 protection applications
— Increases quality of service
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Transmitters
— Transmit waveform shaping meets ITU
G.703 specifications
— Exceeds ETSI ETS 300 166 transmit
return-loss specifications
— Low-impedance transmit drivers,
independent of transmit pattern and
supply-voltage variations
— Low-current transmit output option that
can reduce power dissipation by up to
15%. By changing the LXT385
ransceiver output transformer ratio from
1:2 to 1:1.7, the savings occur whether
TVCC is at 5 V or 3.3 V. 90 mW
per channel (typical). See
Table 62
“Intel
®
LXT385 Transceiver Power
Consumption” on page 104
and
Table 64 “Load
3
Power Consumption”
on page 105.
HDB3 AMI line encoder/decoder
LOS per ITU G.775 and ETS 300 233
Diagnostics:
— Can be configured for G.722-compliant,
non-intrusive performance (protected)
monitoring points
— Industry-standard P1149.1 JTAG
Boundary Scan test port
Intel
®
/ Motorola* 8-bit parallel processor
interface or 4 wire serial control interface
Hardware and Software control modes
Operating temperature -40
°C
to 85
°C
160-ball BGA or 144-pin LQFP packages
Applications
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SDH tributary interfaces
Digital cross connects
Public/private switching trunk line interfaces
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Microwave transmission systems
M13, E1-E3 MUX
Document Number:
249252
Revision Number: 006
Revision Date: 19-Jan-2006
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or
in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
LXT385 Octal E1 Short-Haul Pulse-Code Modulation Transceiver with Jitter Attenuation may contain design defects or errors known as
errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-
548-4725, or by visiting Intel's website at http://www.intel.com.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2001 - 2006 Intel Corporation
2
Datasheet
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Contents
Contents
1.0
Introduction to this Document
............................................................................ 17
1.1
1.2
1.3
Audience and Purpose ........................................................................................ 17
Conventions and Terminology............................................................................. 18
Related Documents............................................................................................. 18
2.0
3.0
4.0
Product Summary
.................................................................................................... 19
Pin Assignments and Package
........................................................................... 22
Multi-Function Pins
.................................................................................................25
4.1
4.2
Operating Mode Multi-Function Pins ................................................................... 25
Framer/Mapper I/O Pins...................................................................................... 27
5.0
Signal Descriptions
.................................................................................................29
5.1
5.2
5.3
Signal Groupings.................................................................................................29
Microprocessor-Standard Bus and Interface Signals .......................................... 30
Framer/Mapper Signals....................................................................................... 33
5.3.1 Bipolar vs. Unipolar Operation - Receive Side ....................................... 33
5.3.2 Bipolar vs. Unipolar Operation - Transmit Side ...................................... 34
5.3.3 Framer/Mapper Signals - Details............................................................ 35
Line Interface Unit Signals .................................................................................. 40
Clocks and Clock-Related Signals ...................................................................... 43
Configuration and Mode-Select Signals .............................................................. 45
Signal Loss and Line-Code-Violation Signals ..................................................... 47
Power and Grounds ............................................................................................49
Test Signals......................................................................................................... 50
5.4
5.5
5.6
5.7
5.8
5.9
6.0
Functional Description
........................................................................................... 51
6.1
6.2
6.3
Functional Overview ............................................................................................52
Initialization and Reset ........................................................................................ 52
Receiver .............................................................................................................. 53
6.3.1 Receiver Clocking .................................................................................. 53
6.3.2 Receiver Inputs ...................................................................................... 53
6.3.3 Receiver Loss-Of-Signal Detector .......................................................... 54
6.3.4 Receiver Data Recovery Mode .............................................................. 55
6.3.5 Receiver Alarm Indication Signal (AIS) Detection .................................. 55
6.3.6 Receive Alarm Indication Signal (RAIS) Enable..................................... 55
6.3.7 Receiver In-Service Line-Code-Violation Monitoring.............................. 56
Transmitter .......................................................................................................... 57
6.4.1 Transmitter Clocking ..............................................................................57
6.4.2 Transmitter Pulse Shaping ..................................................................... 58
6.4.3 Transmitter Outputs................................................................................ 60
6.4.4 Transmitter Output Driver Power and Grounds ...................................... 61
Line-Interface Protection .....................................................................................62
Jitter Attenuation .................................................................................................65
6.4
6.5
6.6
Datasheet
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
3
Contents
6.7
6.8
6.9
6.10
Loopbacks ........................................................................................................... 67
6.7.1 Analog Loopback ................................................................................... 67
6.7.2 Digital Loopback..................................................................................... 68
6.7.3 Remote Loopback .................................................................................. 69
Transmit All Ones Operations ............................................................................. 70
6.8.1 TAOS Generation................................................................................... 70
6.8.2 TAOS Generation with Analog Loopback .............................................. 71
6.8.3 TAOS Generation with Digital Loopback................................................ 71
Performance Monitoring ...................................................................................... 72
Intel
®
Hitless Protection Switching ...................................................................... 73
7.0
Operating Mode Summary
................................................................................... 74
7.1
7.2
7.3
7.4
Interfacing with 5V Logic ..................................................................................... 74
Hardware Mode................................................................................................... 74
Hardware Mode Settings..................................................................................... 75
Host Processor Modes ........................................................................................ 76
7.4.1 Host Processor Mode - Parallel Interface............................................... 76
7.4.2 Host Processor Mode - Serial Interface ................................................. 78
Interrupt Handling................................................................................................ 79
7.5.1 Interrupt Sources.................................................................................... 79
7.5.2 Interrupt Enable...................................................................................... 79
7.5.3 Interrupt Clear ........................................................................................ 79
7.5
8.0
Registers
...................................................................................................................... 80
8.1
8.2
8.3
Register Summary .............................................................................................. 80
Register Addresses ............................................................................................. 82
Register Descriptions .......................................................................................... 83
9.0
JTAG Boundary Scan
............................................................................................. 91
9.1
9.2
9.3
9.4
Overview ............................................................................................................. 91
Architecture ......................................................................................................... 91
TAP Controller..................................................................................................... 92
JTAG Register Description.................................................................................. 94
9.4.1 Boundary Scan Register (BSR).............................................................. 94
9.4.2 Analog Port Scan Register (ASR) .......................................................... 99
9.4.3 Device Identification Register (IDR) ....................................................... 99
9.4.4 Bypass Register (BYR) .......................................................................... 99
9.4.5 Instruction Register (IR) ....................................................................... 100
10.0
11.0
Electrical Characteristics
.................................................................................... 101
Timing Characteristics
......................................................................................... 108
11.1
11.2
Intel
®
LXT385 Transceiver Timing .................................................................... 109
Host Processor Mode - Parallel Interface Timing.............................................. 111
11.2.1 Intel
®
Processor - Parallel Interface Timing ......................................... 111
11.2.2 Motorola* Processor - Parallel Interface Timing................................... 117
Host Processor Mode - Serial Interface Timing ................................................ 123
11.3
4
Datasheet
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Contents
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
Line-Interface-Unit Circuit Specifications
.................................................... 125
Mask Specifications
.............................................................................................. 126
Jitter Performance
................................................................................................. 127
Recommendations and Specifications
.........................................................131
Mechanical Specifications
.................................................................................. 133
16.1
Top Label Markings........................................................................................... 135
Product Ordering Information
........................................................................... 136
Package Information
............................................................................................. 137
Abbreviations and Acronyms
........................................................................... 138
Figures
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25
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28
29
30
31
32
33
Datasheet
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Related Documents............................................................................................. 18
Intel
®
LXT385 Transceiver Package Top-Side Markings .................................... 22
Operating Mode Selections ................................................................................. 25
Operating Mode-Specific Signal Names ............................................................. 26
Receiver Bipolar/Unipolar I/O Signal Functions .................................................. 27
Transmitter Bipolar/Unipolar I/O Signal Functions .............................................. 28
Microprocessor-Standard Bus and Interface Signals .......................................... 30
Framer/Mapper Receive Signals .........................................................................35
Framer/Mapper Transmit Signals........................................................................ 37
Line Interface Unit Signals .................................................................................. 40
Clocks and Clock-Related Signals ...................................................................... 43
Configuration and Mode-Select Signals .............................................................. 45
Signal Loss and Line-Code-Violation Signals ..................................................... 47
Performance-Monitoring Selections with A3:0 Pins ............................................ 48
Power and Grounds ............................................................................................49
JTAG Analog Interface Test Signals ................................................................... 50
JTAG Digital Interface Test Signals .................................................................... 50
Component Values to Use with Transformer Circuit ........................................... 64
Transmitter Transformer Turns Ratio Selection .................................................. 64
Intel
®
LXT385 Transceiver Hardware Mode Settings for Receive, Transmit,
and Loopback...................................................................................................... 75
Host Processor Mode - Parallel Interface Selections .......................................... 76
Intel
®
LXT385 Transceiver Register Summary ................................................... 80
Register Bit Names ............................................................................................. 81
Register Addresses for Serial and Parallel Interfaces......................................... 82
ID Register, ID - 00h............................................................................................83
Analog Loopback Register, ALOOP - 01h...........................................................83
Remote Loopback Register, RLOOP - 02h ......................................................... 83
TAOS Enable Register, TAOS - 03h ................................................................... 83
LOS Status Monitor Register, LOS - 04h ............................................................ 84
DFM Status Monitor Register (05h) for Intel
®
LXT385 Transceiver .................... 84
LOS Interrupt Enable Register, LIE - 06h............................................................ 84
DFM Interrupt Enable Register, DIE (07h) for Intel
®
LXT385 Transceiver.......... 84
LOS Interrupt Status Register, LIS - 08h............................................................. 84
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