PIC24FJ16MC101/102 AND
PIC24FJ32MC101/102/104
16-bit Microcontrollers
(up to 32 KB Flash and 2 KB SRAM)
Operating Conditions
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 16 MIPS
Advanced Analog Features
• ADC module:
- 10-bit, 1.1 Msps with four S&H
- Six analog inputs on 20-pin devices, eight analog
inputs on 28-pin devices, and up to 16 analog inputs
on 44-pin devices
• Flexible and independent ADC trigger sources
• Three Comparator modules
• Charge Time Measurement Unit (CTMU):
- Supports mTouch™ capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
- On-chip temperature measurement
Core: 16-bit PIC24F CPU
•
•
•
•
•
Code-efficient (C and Assembly) architecture
Two 40-bit wide accumulators
Single-cycle (MAC/MPY) with dual data fetch
Single-cycle mixed-sign MUL plus hardware divide
32-bit multiply support
Clock Management
•
•
•
•
•
±0.25% internal oscillator
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast wake-up and start-up
Timers/Output Compare/Input Capture
• Five general purpose timers:
- One 16-bit and two 32-bit timers/counters
• Two Output Compare modules
• Three Input Capture modules
• Peripheral Pin Select (PPS) to allow function remap
Power Management
•
•
•
•
Low-power management modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
1 mA/MHz dynamic current (typical)
30 µA I
PD
current (typical)
Communication Interfaces
• UART module (4 Mbps)
- With support for LIN 2.0 protocols and IrDA
®
• 4-wire SPI module (8 MHz maximum speed)
- Remappable pins in 32 KB Flash devices
• I
2
C™ module (400 kHz)
PWM
Up to three PWM pairs
Two dead time generators
31.25 ns PWM resolution
PWM support for:
- Inverters, PFC, UPS
- BLDC, PMSM, ACIM, SRM
• Class B-compliant Fault inputs
• Possibility of ADC synchronization with PWM signal
•
•
•
•
Input/Output
• Sink/Source 10 mA or 6 mA, on specific for standard
V
OH
/V
OL
, up to 16 mA or 12 mA for non-standard V
OH
1
• 5V-tolerant pins
• Up to 21 open drain, pull-ups, and pull-downs
• External interrupts on most I/O pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC) planned
• Class B Safety Library, IEC 60730, UDE certified
Debugger Development Support
• In-circuit and in-application programming
• Up to three complex data breakpoints
• Trace and run-time watch
Packages
Type
PDIP
SPDIP
SOIC
SSOP
TQFP
Pin Count
20
28
20
28
20
28
44
I/O Pins
15
21
15
21
15
21
35
Contact Lead/Pitch
.100”
.100”
1.27
1.27
0.65
0.65
0.8
Dimensions
Please see
Section 27.2 “Package Details”
for this information.
QFN
28
21
0.65
44
35
0.65
36
21
0.5
VTLA
44
35
0.5
©
2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 1
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
PIC24FJ16MC101/102 AND
PIC24FJ32MC101/102/104 PRODUCT
FAMILIES
The device names, pin counts, memory sizes, and
peripheral availability of each device are listed in
Table 1
and table. The following pages show their
pinout diagrams.
TABLE 1:
PIC24FJ16MC101/102 CONTROLLER FAMILIES
Program Flash (Kbyte)
External Interrupts
(2)
10-Bit, 1.1 Msps ADC
Remappable Peripherals
Remappable Pins
Motor Control PWM
RAM (Kbytes)
Output Compare
16-bit Timer
(1,3)
PWM Faults
Comparators
Input Capture
PIC24FJ16MC101
20
16
1
10
3
3
2
1
3
SPI
Device
UART
1
6-ch
1
1 ADC,
4-ch
1 ADC,
6-ch
1 ADC,
6-ch
Y
1
3
Y
15
PDIP,
SOIC,
SSOP
SPDIP,
SOIC,
SSOP,
QFN
VTLA
PIC24FJ16MC102
28
16
1
16
3
3
2
1
3
1
6-ch
2
Y
1
3
Y
21
36
Note 1:
2:
3:
16
1
16
3
3
2
1
3
1
6-ch
2
Y
1
3
Y
21
Two out of three timers are remappable.
Two out of three interrupts are remappable.
One pair can be combined to create a 32-bit timer.
TABLE 2:
PIC24FJ32MC101/102/104 CONTROLLER FAMILIES
Program Flash (Kbyte)
External Interrupts
(2)
10-Bit, 1.1 Msps ADC
Remappable Peripherals
Remappable Pins
Motor Control PWM
RAM (Kbytes)
Output Compare
16-bit Timer
(1,3)
PWM Faults
Comparators
Input Capture
PIC24FJ32MC101
20
32
2
10
5
3
2
1
3
SPI
Device
UART
1
6-ch
1
1 ADC,
6-ch
1 ADC,
8-ch
1 ADC,
8-ch
14
Y
1
3
Y
15
PDIP,
SOIC,
SSOP
SPDIP,
SOIC,
SSOP,
QFN
VTLA
TQFP,
QFN,
VTLA
PIC24FJ32MC102
28
32
2
16
5
3
2
1
3
1
6-ch
2
Y
1
3
Y
21
36
PIC24FJ32MC104
44
32
32
2
2
16
26
5
1
3
3
2
2
1
1
3
3
1
1
6-ch
6-ch
2
2
Y
Y
1
1
3
3
Y
Y
21
35
Note 1:
2:
3:
Two out of three timers are remappable.
Two out of three interrupts are remappable.
Two pairs can be combined to create two 32-bit timers.
DS39997C-page 2
Preliminary
©
2011-2012 Microchip Technology Inc.
Packages
I/O Pins
CTMU
RTCC
I
2
C™
Pins
Packages
I/O Pins
CTMU
RTCC
I
2
C™
Pins
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
Pin Diagrams
20-Pin PDIP/SOIC/SSOP
= Pins are up to 5V tolerant
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
PGEC1/AN3/CV
REFIN
/CV
REFOUT
/C2INB/C1IND/RP1
(1)
/CN5/RB1
V
SS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/RP4
(1)
/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
V
SS
PWM1L1/RP15
(1)
/CN11/RB15
PWM1H1/RTCC/RP14
(1)
/CN12/RB14
PWM1L2/RP13
(1)
/CN13/RB13
PWM1H2/RP12
(1)
/CN14/RB12
V
CAP
SDA1/SDI1/PWM1L3/RP9
(1)
/CN21/RB9
SCL1/SDO1/PWM1H3/RP8
(1)
/CN22/RB8
FLTA1
(2)
/SCK1/INT0/RP7
(1)
/CN23/RB7
PIC24FJ16MC101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
PGEC1/AN3/CV
REFIN
/CV
REFOUT
/C2INB/C1IND/RP1
(1)
/CN5/RB1
V
SS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/AN9/RP4
(1)
/CN1/RB4
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
V
SS
PWM1L1/RP15
(1)
/CN11/RB15
PWM1H1/RTCC/RP14
(1)
/CN12/RB14
PWM1L2/RP13
(1)
/CN13/RB13
PWM1H2/RP12
(1)
/CN14/RB12
V
CAP
SDA1/PWM1L3/RP9
(1)
/CN21/RB9
SCL1/PWM1H3/RP8
(1)
/CN22/RB8
FLTA1
(2)
/INT0/RP7
(1)
/CN23/RB7
Note 1:
The RPn pins can be used by any remappable peripheral. See
Table 1
for the list of available
peripherals.
2:
The PWM Fault pins are enabled and asserted during any reset event. Refer to
Section 15.2
“PWM Faults”
for more information on the PWM faults.
©
2011-2012 Microchip Technology Inc.
Preliminary
PIC24FJ32MC101
DS39997C-page 3
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
Pin Diagrams (Continued)
28-Pin SPDIP/SOIC/SSOP
= Pins are up to 5V tolerant
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
PGEC1/AN3/CV
REFIN
/CV
REFOUT
/C2INB/C1IND/RP1
(1)
/CN5/RB1
AN4/C3INC/C2INC/RP2
(1)
/CN6/RB2
AN5/C3IND/C2IND/RP3
(1)
/CN7/RB3
V
SS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/RP4
(1)
/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
V
DD
FLTB1
(2)
/ASDA1/RP5
(1)
/CN27/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
DD
AV
SS
PWM1L1/RP15
(1)
/CN11/RB15
PWM1H1/RTCC/RP14
(1)
/CN12/RB14
PWM1L2/RP13
(1)
/CN13/RB13
PWM1H2/RP12
(1)
/CN14/RB12
PWM1L3/RP11
(1)
/CN15/RB11
PWM1H3/RP10
(1)
/CN16/RB10
V
CAP
V
SS
SDA1/SDI1/RP9
(1)
/CN21/RB9
SCL1/SDO1/RP8
(1)
/CN22/RB8
SCK1/INT0/RP7
(1)
/CN23/RB7
FLTA1
(2)
/ASCL1/RP6
(1)
/CN24/RB6
PIC24FJ16MC102
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
PGEC1/AN3/CV
REFIN
/CV
REFOUT
/C2INB/C1IND/RP1
(1)
/CN5/RB1
AN4/C3INC/C2INC/RP2
(1)
/CN6/RB2
AN5/C3IND/C2IND/RP3
(1)
/CN7/RB3
V
SS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/AN9/RP4
(1)
/CN1/RB4
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
V
DD
(2)
(1)
FLTB1 /ASDA1/RP5 /CN27/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
DD
AV
SS
PWM1L1/RP15
(1)
/CN11/RB15
PWM1H1/RTCC/RP14
(1)
/CN12/RB14
PWM1L2/RP13
(1)
/CN13/RB13
PWM1H2/RP12
(1)
/CN14/RB12
PWM1L3/RP11
(1)
/CN15/RB11
PWM1H3/RP10
(1)
/CN16/RB10
V
CAP
V
SS
SDA1/RP9
(1)
/CN21/RB9
SCL1/RP8
(1)
/CN22/RB8
INT0/RP7
(1)
/CN23/RB7
FLTA1
(2)
/ASCL1/RP6
(1)
/CN24/RB6
Note 1:
The RPn pins can be used by any remappable peripheral. See
Table 1
for the list of available
peripherals.
2:
The PWM Fault pins are enabled and asserted during any reset event. Refer to
Section 15.2
“PWM Faults”
for more information on the PWM faults.
DS39997C-page 4
Preliminary
PIC24FJ32MC102
©
2011-2012 Microchip Technology Inc.
PIC24FJ16MC101/102 AND PIC24FJ32MC101/102/104
Pin Diagrams (Continued)
28-Pin QFN
(2)
= Pins are up to 5V tolerant
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
28 27 26 25 24 23 22
PGED1/AN2/C2INA/C1INC/CTCMP/RP0 /CN4/RB0
PGEC1/AN3/CV
REFIN
/CV
REFOUT
/C2INB/C1IND/RP1
(1)
/CN5/RB1
AN4/C3INC/C2INC/RP2
(1)
/CN6/RB2
AN5/C3IND/C2IND/RP3
(1)
/CN7/RB3
V
SS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
(1)
PWM1H1/RTCC/RP14
(1)
/CN12/RB14
PWM1L1/RP15
(1)
/CN11/RB15
MCLR
AV
DD
AV
SS
1
2
3
4
5
6
7
8
PGED3/SOSCI/RP4
(1)
/CN1/RB4
9 10 11 12 13 14
FLTB1
(3)
/ASDA1/RP5
(1)
/CN27/RB5
FLTA1
(3)
/ASCL1/RP6
(1)
/CN24/RB6
SCK1/INT0/RP7
(1)
/CN23/RB7
PGEC3/SOSCO/T1CK/CN0/RA4
SCL1/SDO1/RP8
(1)
/CN22/RB8
V
DD
21
20
19
PWM1L2/RP13
(1)
/CN13/RB13
PWM1H2/RP12
(1)
/CN14/RB12
PWM1L3/RP11
(1)
/CN15/RB11
PWM1H3/RP10
(1)
/CN16/RB10
V
CAP
V
SS
SDA1/SDI1/RP9
(1)
/CN21/RB9
PIC24FJ16MC102
18
17
16
15
Note 1:
The RPn pins can be used by any remappable peripheral. See
Table 1
for the list of available
peripherals.
2:
The metal pad at the bottom of the device is not connected to any pins and is recommended to be
connected to V
SS
externally.
3:
The PWM Fault pins are enabled and asserted during any reset event. Refer to
Section 15.2
“PWM Faults”
for more information on the PWM faults.
©
2011-2012 Microchip Technology Inc.
Preliminary
DS39997C-page 5
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