XWM8192 datasheet, PDF - EEWORLD Datasheet

WM8192

(8 + 8) Bit Output 16-bit CIS/CCD AFE/Digitiser

Product Preview, June 2000, Rev 1.0

DESCRIPTION

The WM8192 is a 16-bit analogue front end/digitiser IC

which processes and digitises the analogue output signals

from CCD sensors or Contact Image Sensors (CIS) at pixel

sample rates of up to 6MSPS.

The device includes three analogue signal processing

channels each of which contains Reset Level Clamping,

Correlated Double Sampling and Programmable Gain and

Offset adjust functions. Three multiplexers allow single

channel processing. The output from each of these

channels is time multiplexed into a single high-speed 16-bit

Analogue to Digital Converter. The digital output data is

available in 8 or 4-bit wide multiplexed format.

An internal 4-bit DAC is supplied for internal reference level

generation. This may be used during CDS to reference CIS

signals or during Reset Level Clamping to clamp CCD

signals. An external reference level may also be supplied.

ADC references are generated internally, ensuring optimum

performance from the device.

Using an analogue supply voltage of 5V and a digital

interface supply of either 5V or 3.3V, the WM8192 typically

only consumes 240mW when operating from a single

5V supply.

FEATURES

•

16-bit ADC

6MSPS conversion rate

Low power – 240mW typical

5V single supply or 5V/3.3V dual supply operation

Single or 3 channel operation

Correlated double sampling

Programmable gain (8-bit resolution)

Programmable offset adjust (8-bit resolution)

Programmable clamp voltage

8 or 4-bit wide multiplexed data output formats

Internally generated voltage references

28-pin SOIC package

Serial control interface

APPLICATIONS

•

Flatbed and sheetfeed scanners

USB compatible scanners

Multi-function peripherals

High-performance CCD sensor interface

BLOCK DIAGRAM

VRLC/VBIAS

(26)

VSMP

(5)

MCLK

(7)

AVDD

(21)

DVDD1 DVDD2

(10)

(3)

VRT VRX VRB

(24) (25) (23)

CL

R

S

V

S

TIMING CONTROL

R

G

B

VREF/BIAS

M

U

X

8

WM8192

(4) OEB

OFFSET

DAC

+

PGA

8

RINP (1)

RLC

M

U

X

CDS

R

G

B

M

U

X

+

I/P SIGNAL

POLARITY

ADJUST

M

U

X

16-

BIT

ADC

DATA

I/O

PORT

(13) OP[0]

(14) OP[1]

(15) OP[2]

(16) OP[3]

(17) OP[4]

(18) OP[5]

(19) OP[6]

(20) OP[7]/SDO

GINP (28)

RLC

CDS

8

+

OFFSET

DAC

PGA

8

+

I/P SIGNAL

POLARITY

ADJUST

BINP (27)

RLC

CDS

8

+

OFFSET

DAC

PGA

8

+

I/P SIGNAL

POLARITY

ADJUST

RLC

DAC

4

CONFIGURABLE

SERIAL

CONTROL

INTERFACE

(9) SEN

(12) SCK

(11) SDI

(6) RLC/ACYC

(22)

AGND1

(2)

AGND2

(8)

DGND

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK

Tel: +44 (0) 131 667 9386

Fax: +44 (0) 131 667 5176

Email: sales@wolfson.co.uk

http://www.wolfson.co.uk

Product Preview

data sheets contain

specifications for products in the formative

phase of development. These products may

be changed or discontinued without notice.

2000

Wolfson Microelectronics Ltd

.

WM8192

PIN CONFIGURATION

RINP

AGND2

DVDD1

OEB

VSMP

RLC/ACYC

MCLK

DGND

SEN

DVDD2

SDI

SCK

OP[0]

OP[1]

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GINP

BINP

VRLC/VBIAS

VRX

VRT

VRB

AGND1

AVDD

OP[7]/SDO

OP[6]

OP[5]

OP[4]

OP[3]

OP[2]

Product Preview

ORDERING INFORMATION

DEVICE

XWM8192CDW/V

TEMP. RANGE

0 to 70

o

C

PACKAGE

28-pin SOIC

PIN DESCRIPTION

1

2

3

4

5

6

7

8

9

10

11

12

NAME

RINP

AGND2

DVDD1

OEB

VSMP

RLC/ACYC

MCLK

DGND

SEN

DVDD2

SDI

SCK

TYPE

Analogue input

Supply

Digital input

Supply

Digital input

Supply

Digital input

DESCRIPTION

Red channel input video.

Analogue ground (0V).

Digital supply (5V) for logic and clock generator. This must be operated at the same

potential as AVDD.

Output Hi-Z control, all digital outputs disabled when OEB = 1.

Video sample synchronisation pulse.

RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if

used on every pixel. ACYC autocycles between R, G, B inputs.

Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or

any multiple of 2 thereafter depending on input sample mode).

Digital ground (0V).

Enables the serial interface when high.

Digital supply (5V/3.3V), all digital I/O pins.

Serial data input.

Serial clock.

Digital multiplexed output data bus.

ADC output data (d15:d0) is available in two multiplexed formats as shown, under

the control of register bit MUXOP.

See ‘Output Formats’ description in Device Description section for further details.

8+8-bit

A

13

14

15

16

17

18

19

20

OP[0]

OP[1]

OP[2]

OP[3]

OP[4]

OP[5]

OP[6]

OP[7]

Digital output

d8

d9

d10

d11

d12

d13

d14

d15

B

d0

d1

d2

d3

d4

d5

d6

d7

d12

d13

d14

d15

d8

d9

d10

d11

d4

d5

d6

d7

d0

d1

d2

d3

A

B

4+4+4+4-bit

C

D

Alternatively, pin OP[7]/SDO may be used to output register read-back data when

OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device

Description section for further details.

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 June 2000

2

Product Preview

21

22

23

24

25

26

NAME

AVDD

AGND1

VRB

VRT

VRX

VRLC/VBIAS

TYPE

Supply

Analogue output

Analogue I/O

DESCRIPTION

WM8192

Analogue supply (5V). This must be operated at the same potential as DVDD1.

Analogue ground (0V).

Lower reference voltage.

This pin must be connected to AGND via a decoupling capacitor.

Upper reference voltage.

This pin must be connected to AGND via a decoupling capacitor.

Input return bias voltage.

This pin must be connected to AGND via a decoupling capacitor.

Selectable analogue output voltage for RLC or single-ended bias reference.

This pin would typically be connected to AGND via a decoupling capacitor.

VRLC can be externally driven if programmed Hi-Z.

Blue channel input video.

Green channel input video.

27

28

BINP

GINP

Analogue input

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at

or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible

to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage

of this device.

As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount

assembly. It is anticipated as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture

barrier bags.

CONDITION

Analogue supply voltage: AVDD

Digital supply voltages: DVDD1

−

2

Digital ground: DGND

Analogue grounds: AGND1

−

2

Digital inputs, digital outputs and digital I/O pins

Analogue inputs (RINP, GINP, BINP)

Other pins

Operating temperature range: T

A

Storage temperature

Package body temperature (soldering, 10 seconds)

Package body temperature (soldering, 2 minutes)

Notes:

1.

2.

GND denotes the voltage of any ground pin.

AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages

between these pins will degrade performance.

MIN

GND - 0.3V

0

°

C

-65

°

C

MAX

GND + 7V

GND + 0.3V

DVDD2 + 0.3V

AVDD + 0.3V

+70

°

C

+150

°

C

+240

°

C

+183°C

RECOMMENDED OPERATING CONDITIONS

CONDITION

Operating temperature range

Analogue supply voltage

Digital core supply voltage

Digital I/O supply voltage

5V I/O

3.3V I/O

SYMBOL

T

A

AVDD

DVDD1

DVDD2

MIN

0

4.75

2.97

5.0

3.3

TYP

MAX

70

5.25

3.63

UNITS

°C

V

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 June 2000

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WM8192

ELECTRICAL CHARACTERISTICS

Product Preview

Test Conditions

AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, T

A

= 0 to 70°C, MCLK = 12MHz unless otherwise stated.

PARAMETER

SYMBOL

TEST

CONDITIONS

Max Gain

Min Gain

V

IN

Gain = 0dB;

PGA[7:0] = 4B(hex)

Gain = 0dB;

PGA[7:0] = 4B(hex)

DNL

INL

0

20

TBD

1

VRT

VRB

VRX

V

RTB

2.85

1.35

0.65

1.5

1

50

5

2

VRLC = 0 to AVDD

4

V

RLCSTEP

V

RLCSTEP

V

RLCBOT

V

RLCBOT

V

RLCTOP

V

RLCTOP

-50

8

DNL

INL

Code 00(hex)

Code FF(hex)

0.1

0.25

2.04

-260

+260

0.5

1

0.24

0.16

0.40

0.25

4.20

2.85

+50

1

MIN

TYP

MAX

UNIT

Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)

Full-scale input voltage range

(see Note 1)

Input signal limits (see Note 2)

Full-scale transition error

Zero-scale transition error

Differential non-linearity

Integral non-linearity

Channel to channel gain matching

References

Upper reference voltage

Lower reference voltage

Input return bias voltage

Diff. reference voltage (VRT-VRB)

Output resistance VRT, VRB, VRX

VRLC/Reset-Level Clamp (RLC)

RLC switching impedance

VRLC short-circuit current

VRLC output resistance

VRLC Hi-Z leakage current

RLCDAC resolution

RLCDAC step size, RLCDAC = 0

RLCDAC step size, RLCDAC = 1

RLCDAC output voltage at

code 0(hex), RLCDACRNG = 0

RLCDAC output voltage at

code 0(hex), RLCDACRNG = 1

RLCDAC output voltage at

code F(hex) RLCDACRNG, = 0

RLCDAC output voltage at

code F(hex), RLCDACRNG = 1

VRLC deviation

Offset DAC, Monotonicity Guaranteed

Resolution

Differential non-linearity

Integral non-linearity

Step size

Output voltage

bits

LSB

mV/step

mV

Ω

mA

Ω

µA

bits

V/step

V

mV

V

Ω

0.4

4.08

AVDD

Vp-p

V

mV

LSB

%

Notes:

1.

Full-scale input voltage

denotes the maximum amplitude of the input signal at the specified gain.

2.

Input signal limits

are the limits within which the full-scale input voltage signal must lie.

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 June 2000

4

Product Preview

WM8192

Test Conditions

AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, T

A

= 0 to 70°C, MCLK = 12MHz unless otherwise stated.

PARAMETER

Programmable Gain Amplifier

Resolution

Gain

Max gain, each channel

Min gain, each channel

Gain error, each channel

DIGITAL SPECIFICATIONS

Digital Inputs

High level input voltage

Low level input voltage

High level input current

Low level input current

Input capacitance

Digital Outputs

High level output voltage

Low level output voltage

High impedance output current

Digital IO Pins

Applied high level input voltage

Applied low level input voltage

High level output voltage

Low level output voltage

Low level input current

High level input current

Input capacitance

High impedance output current

Supply Currents

Total supply current

−

active

Total analogue supply current

−

active

Digital core supply current,

DVDD1

−

active

Digital I/O supply current,

DVDD2

−

active

Supply current

−

full power down

mode

I

AVDD

48

45

2

1

100

mA

µA

V

IH

V

IL

V

OH

V

OL

I

IL

I

IH

C

I

OZ

5

1

I

OH

= 1mA

I

OL

= 1mA

DVDD2 - 0.5

0.5

1

0.8

∗

DVDD2

0.2

∗

DVDD2

V

µA

pF

µA

V

OH

V

OL

I

OZ

I

OH

= 1mA

I

OL

= 1mA

DVDD2 - 0.5

0.5

1

V

µA

V

IH

V

IL

I

IH

I

IL

C

I

5

0.8

∗

DVDD2

0.2

∗

DVDD2

1

V

µA

pF

G

MAX

G

MIN

8

208

283

−

PGA[7 : 0]

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

bits

V/V

%

7.4

0.74

1

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 June 2000

5

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