• 2.7 to 3.6 volt for read, erase, and program operations
• Dual Output Mode (DREAD)
• Auto Erase and Auto Program Algorithm
• HOLD FEATURE
P/N: PM1669
1
Rev. 1.4, July 21, 2016
MX25L512E
Contents
FEATURES .................................................................................................................................................................. 4
GENERAL .......................................................................................................................................................... 4
SOFTWARE FEATURES ................................................................................................................................... 4
GENERAL DESCRIPTION ......................................................................................................................................... 5
DATA PROTECTION.................................................................................................................................................... 8
Table 1. Protected Area Sizes ............................................................................................................................ 9
HOLD FEATURE.......................................................................................................................................................... 9
Figure 1. Hold Condition Operation ................................................................................................................... 9
(4) Read Status Register (RDSR) .................................................................................................................... 13
Status Register ................................................................................................................................................. 13
(5) Write Status Register (WRSR).................................................................................................................... 14
(12) Page Program (PP)................................................................................................................................... 16
(13) Deep Power-down (DP) ............................................................................................................................ 17
(14) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 17
(15) Read Electronic Manufacturer ID & Device ID (REMS) ............................................................................ 18
POWER-ON STATE ................................................................................................................................................... 25
At Device Power-Up ......................................................................................................................................... 40
Figure 28. AC Timing at Device Power-Up ....................................................................................................... 40
ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 42
DATA RETENTION .................................................................................................................................................... 42
ORDERING INFORMATION ...................................................................................................................................... 43
PART NAME DESCRIPTION ..................................................................................................................................... 44
PACKAGE INFORMATION ........................................................................................................................................ 45
REVISION HISTORY ................................................................................................................................................. 48
P/N: PM1669
3
Rev. 1.4, July 21, 2016
MX25L512E
512K-BIT [x 1/x 2] CMOS SERIAL FLASH
FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
• 524,288 x 1 bit structure or 262,144 x 2 bits (Dual
Output mode) Structure
• 16 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 104MHz serial clock
- Serial clock of Dual Output mode: 80MHz
- Fast program time: 0.6ms(typ.) and 3ms(max.)/
page (256-byte per page)
- Byte program time: 9us
- Fast erase time: 40ms(typ.)/sector (4K-byte per
sector); 0.4s(typ.) and 2s(max.)/chip
• Low Power Consumption
- Low active read current: 12mA(max.) at 104MHz
and 4mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 9mA (typ.)
- Low standby current: 15uA (typ.)
- Deep power-down mode 2uA (typ.)
• Minimum 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bit defines the size of the
area to be software protected against Program and
Erase instructions.
• Auto Erase and Auto Program Algorithm
sector
-
Automatically erases and verifies data at selected
ed page by an internal algorithm that automatically
times the program pulse widths (Any page to be pro-
gramed should have page in the erased state first)
•
Status Register Feature
•
Electronic Identification
- RES command, 1-byte Device ID
•
Support Serial Flash Discoverable Parameters (SFDP)
mode
HARDWARE FEATURES
•
SCLK Input
• SI/SIO0
- Serial Data Input or Serial Data Output for Dual
output mode
• SO/SIO1
- Serial Data Output or Serial Data Output for Dual
output mode
• WP# pin
- Hardware Write Protection
• HOLD# pin
- Pause the chip without diselecting the chip
• PACKAGE
- 8-pin SOP (150mil)
- 8-USON (2x3mm)
- 8-pin TSSOP (173mil)
-
All devices are RoHS Compliant and Halogen-
free
-
Automatically programs and verifies data at select-
-
JEDEC 2-byte Device ID
-
Serial clock input
P/N: PM1669
4
Rev. 1.4, July 21, 2016
MX25L512E
GENERAL DESCRIPTION
MX25L512E is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. MX25L512E
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
MX25L512E provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and
erase command is executes on chip or sector (4K-bytes).
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L512E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
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