Datasheet
Serial EEPROM Series Standard EEPROM
I
2
C BUS EEPROM (2-Wire)
BR24Gxxx-3A (128K 256K 1M)
General Description
BR24Gxxx-3A is a serial EEPROM of I
2
C BUS Interface Method
Features
All controls available by 2 ports of serial clock(SCL) and
serial data(SDA)
Other devices than EEPROM can be connected to the
same port, saving microcontroller port
1.7V to 5.5V Single Power Source Operation most
suitable for battery use
1.7V to 5.5V wide limit of operating voltage, possible
1MHz operation
Page Write Mode useful for initial value write at factory
shipment
Self-timed Programming Cycle
Low Current Consumption
Prevention of Write Mistake
Write (Write Protect) Function added
Prevention of Write Mistake at Low Voltage
More than 1 million write cycles
More than 40 years data retention
Noise filter built in SCL / SDA terminal
Initial delivery state FFh
Packages
W(Typ) x D(Typ)x H(Max)
DIP-T8
9.30mm x 6.50mm x 7.10mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
SOP8
5.00mm x 6.20mm x 1.71mm
TSSOP-B8J
3.00mm x 4.90mm x 1.10mm
SOP-J8
4.90mm x 6.00mm x 1.65mm
MSOP8
2.90mm x 4.00mm x 0.90mm
SSOP-B8
3.00mm x 6.40mm x 1.35mm
VSON008X2030
2.00mm x 3.00mm x 0.60mm
Figure 1.
Page Write
Number of Pages
Product Number
64Byte
BR24G128-3A
BR24G256-3A
256Byte
BR24G1M-3A
BR24G128-3A
Capacity
Bit Format
Type
BR24G128-3A
BR24G128F-3A
BR24G128FJ-3A
BR24G128FV-3A
128kbit
16k×8
BR24G128FVT-3A
BR24G128FVJ-3A
BR24G128FVM-3A
BR24G128NUX-3A
1.7V to 5.5V
TSSOP-B8
TSSOP-B8J
MSOP8
VSON008X2030
Power Source
Voltage
Package
DIP-T8
SOP8
SOP-J8
SSOP-B8
○
Product structure：Silicon monolithic integrated circuit
○This
product has no designed protection against radioactive rays
.
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TSZ22111・14・001
BR24Gxxx-3A (128K 256K 1M)
BR24G256-3A
Capacity
Bit Format
Type
BR24G256-3A
BR24G256F-3A
256kbit
32k×8
BR24G256FJ-3A
BR24G256FV-3A
BR24G256FVT-3A
1.7V to 5.5V
Power Source
Voltage
Package
DIP-T8
SOP8
SOP-J8
SSOP-B8
TSSOP-B8
BR24G1M-3A
Capacity
Bit Format
Type
BR24G1M-3A
1Mbit
128k×8
BR24G1MF-3A
BR24G1MFJ-3A
1.7V to 5.5V
Power Source
Voltage
Package
DIP-T8
SOP8
SOP-J8
.
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BR24Gxxx-3A (128K 256K 1M)
Absolute Maximum Ratings (Ta=25°C)
Parameter
Supply Voltage
Symbol
Vcc
Rating
-0.3 to +6.5
0.45 (SOP8)
0.45 (SOP-J8)
0.30 (SSOP-B8)
Power Dissipation
Pd
0.33 (TSSOP-B8)
0.31 (TSSOP-B8J)
0.31 (MSOP8)
0.30 (VSON008X2030)
0.80 (DIP-T8)
Storage Temperature
Operating Temperature
Input Voltage /
Output Voltage
Junction
Temperature
Electrostatic discharge
voltage
(human body model)
Tstg
Topr
‐
Tjmax
V
ESD
-65 to +150
-40 to +85
-0.3 to Vcc+1.0
150
-4000 to +4000
°C
°C
V
°C
V
The Max value of Input Voltage/Output Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value Input
Voltage/Output Voltage is not lower than -1.0V.
Junction temperature at the storage condition
Unit
V
Remark
Derate by 4.5mW/°C when operating above Ta=25°C
Derate by 4.5mW/°C when operating above Ta=25°C
Derate by 3.0mW/°C when operating above Ta=25°C
W
Derate by 3.3mW/°C when operating above Ta=25°C
Derate by 3.1mW/°C when operating above Ta=25°C
Derate by 3.1mW/°C when operating above Ta=25°C
Derate by 3.0mW/°C when operating above Ta=25°C
Derate by 8.0mW/°C when operating above Ta=25°C
Memory Cell Characteristics (Ta=25°C, Vcc=1.7V to 5.5V)
Parameter
Write Cycles
(1)
Data Retention
(1)
(1) Not 100% TESTED
Min
1,000,000
40
Limit
Typ
-
-
Max
-
-
Unit
Times
Years
Recommended Operating Ratings
Parameter
Power Source Voltage
Input Voltage
Symbol
Vcc
V
IN
Rating
1.7 to 5.5
0 to Vcc
Unit
V
DC Characteristics (Unless otherwise specified, Ta=-40°C to +85°C, Vcc =1.7V to 5.5V)
Parameter
Input High Voltage 1
Input Low Voltage 1
Output Low Voltage 1
Output Low Voltage 2
Input Leakage Current
Output Leakage Current
Symbol
V
IH1
V
IL1
V
OL1
V
OL2
I
LI
I
LO
Limit
Min
0.7Vcc
-0.3
(2)
-
-
-1
-1
-
Supply Current (Write)
I
CC1
-
Supply Current (Read)
I
CC2
-
-
-
4.5
2.0
mA
Typ
-
-
-
-
-
-
-
Max
Vcc+1.0
+0.3Vcc
0.4
0.2
+1
+1
2.5
mA
Unit
V
V
V
V
μA
μA
I
OL
=3.0mA,
2.5V≦Vcc≦5.5V (SDA)
I
OL
=0.7mA,
1.7V≦Vcc＜2.5V (SDA)
V
IN
=0 to Vcc
V
OUT
=0 to Vcc (SDA)
V
CC
=5.5V, f
SCL
=1MHz, t
WR
=5ms,
Byte write, Page write
BR24G128/256-3A
V
CC
=5.5V, f
SCL
=1MHz, t
WR
=5ms,
Byte write, Page write
BR24G1M-3A
V
CC
=5.5V, f
SCL
=1MHz
Random read, current read,
sequential read
V
CC
=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
BR24G128/256-3A
V
CC
=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
BR24G1M-3A
Conditions
-
Standby Current
I
SB
-
(2) When the pulse width is 50ns or less, it is -1.0V.
-
2.0
μA
-
3.0
.
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BR24Gxxx-3A (128K 256K 1M)
AC Characteristics
(Unless otherwise specified, Ta=-40°C to +85°C, Vcc=1.7V to 5.5V)
Parameter
Clock Frequency
Data Clock “HIGH“ Period
Data Clock “LOW“ Period
SDA, SCL (INPUT) Rise Time
(1)
SDA, SCL (INPUT) Fall Time
(1)
SDA (OUTPUT) Fall Time
(1)
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time
Output Data Dold Time
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA, SCL)
WP Hold Time
WP Setup Time
WP High Period
(1) Not 100% tested
Symbol
f
SCL
t
HIGH
t
LOW
t
R
t
F1
t
F2
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
PD
t
DH
t
SU:STO
t
BUF
t
WR
t
I
t
HD:WP
t
SU:WP
t
HIGH:WP
Limit
Min
-
0.30
0.5
-
-
-
0.25
0.20
0
50
0.05
0.05
0.25
0.5
-
-
1.0
0.1
1.0
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
1000
-
-
0.12
0.12
0.12
-
-
-
-
0.45
-
-
-
5
0.05
-
-
-
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
µs
µs
µs
AC Characteristics Condition
Parameter
Load Capacitance
SDA, SCL (INPUT) Rise Time
SDA, SCL (INPUT) Fall Time
Input Data Level
Input/Output Data Timing Reference Level
Symbol
C
L
t
R
t
F1
V
IL1
/V
IH1
-
Conditions
100
20
20
0.2V
CC
/0.8Vcc
0.3V
CC
/0.7Vcc
Unit
pF
ns
ns
V
V
.
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BR24Gxxx-3A (128K 256K 1M)
Serial Input / Output Timing
tR
SCL
70%
30%
70% 70%
30%
tF1
tHIGH
70%
30%
70%
30%
tHD:STA
70%
70%
30%
70%
tLOW
tSU:DAT
tHD:DAT
70%
30%
SDA
(入力)
(INPUT)
SDA
(出力)
(OUTPUT)
tBUF
tPD
70%
30%
tDH
70%
30%
30%
○Input
read at the rise edge of SCL
○Data
output in sync with the fall of SCL
tF2
Figure 2-(a). Serial Input / Output Timing
70%
70%
70%
tSU:STA
70%
30%
tHD:STA
tSU:STO
30%
START CONDITION
STOP CONDITION
Figure 2-(b). Start-Stop Bit Timing
D0
write data
(n-th address)
ACK
70%
70%
tWR
STOP CONDITION
START CONDITION
Figure 2-(c). Write Cycle Timing
70%
DATA(1)
D1
D0
ACK
DATA(n)
ACK
70%
tWR
30%
30%
tSU:WP
tHD:WP
STOP CONDITION
Figure 2-(d). WP Timing at Write Execution
DATA(1)
D1
D0
ACK
DATA(n)
ACK
tHIGH:WP
70%
70%
70%
tWR
Figure 2-(e). WP Timing at Write Cancel
.
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PCB Design
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