b. Pulse width limited by maximum junction temperature.
b
Symbol
V
DS
V
GS
T
A
= 25 °C
T
A
= 100 °C
T
A
= 25 °C
T
A
= 100 °C
I
D
I
DM
P
D
R
thJA
T
J,
T
stg
Limit
- 60
± 20
- 185
- 115
- 800
350
140
350
- 55 to 150
Unit
V
mA
mW
°C/W
°C
1
SPECIFICATIONS
T
A
= 25 °C, unless otherwise noted
Limits
Parameter
Static
Drain-Source Breakdown Voltage
Gate-Threshold Voltage
V
DS
V
GS(th)
V
GS
= 0 V, I
D
= - 10 µA
V
DS
= V
GS
, I
D
= - 250 µA
V
DS
= 0 V, V
GS
= ± 20 V
Gate-Body Leakage
I
GSS
V
DS
= 0 V, V
GS
= ± 10 V
V
DS
= 0 V, V
GS
= ± 10 V, T
J
= 85 °C
V
DS
= 0 V, V
GS
= ± 5 V
Zero Gate Voltage Drain Current
On-State Drain Current
a
I
DSS
I
D(on)
V
DS
= - 60 V, V
GS
= 0 V
V
DS
= - 60 V, V
GS
= 0 V, T
J
= 85 °C
V
GS
= - 10 V, V
DS
= - 4.5 V
V
GS
= - 10 V, V
DS
= - 10 V
V
GS
= - 4.5 V, I
D
= - 25 mA
Drain-Source On-Resistance
a
Forward Transconductance
a
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching
b
Turn-On Time
Turn-Off Time
t
d(on)
t
d(off)
V
DD
= - 25 V, R
L
= 150
I
D
- 200 mA, V
GEN
= - 10 V, R
g
= 10
20
35
ns
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
1.7
V
DS
= - 30 V, V
GS
= - 15 V
I
D
- 500 mA
0.26
0.46
23
V
DS
= - 25 V, V
GS
= 0 V
f = 1 MHz
10
5
pF
nC
R
DS(on)
g
fs
V
SD
V
GS
= - 10 V, I
D
= - 500 mA
V
GS
= - 10 V, I
D
= - 500 mA, T
J
=125 °C
V
DS
= - 10 V, I
D
= - 100 mA
I
S
= - 200 mA, V
GS
= 0 V
80
- 1.4
- 50
- 600
10
6
9
mS
V
- 60
-1
-3
± 10
± 200
± 500
± 100
- 25
- 250
mA
nA
V
µA
Symbol
Test Conditions
Min.
Typ.
a
Max.
Unit
Notes:
a. Pulse test: PW
300 µs duty cycle
2 %.
b. Switching time is essentially independent of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
process(rstn,clk25m) begin if rstn='0' then d1'0'); elsif clk25m'event and clk25m='1' then if d1='1' and d2='0' then SCS_N<= SCS; testdata<=testdata+1; end if; end if; end process; Wrote the above cod...
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FPGA/CPLD
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