Preliminary
GS8161V18B(T/D)/GS8161V32B(D)/GS8161V36B(T/D)
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard
100-lead TQFP
and 165-bump BGA packages
• Pb-Free 100-lead TQFP package available
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
250 MHz–150 MHz
1.8 V V
DD
1.8 V I/O
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode pin (Pin 14). Holding the FT mode pin low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered Data
Output Register.
SCD Pipelined Reads
The GS8161V18B(T/D)/GS8161V32B(D)/GS8161V36B(T/D) is
a SCD (Single Cycle Deselect) pipelined synchronous SRAM.
DCD (Dual Cycle Deselect) versions are also available. SCD
SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS8161V18B(T/D)/GS8161V32B(D)/GS8161V36B(T/D)
operates on a 1.8 V power supply. All input are 1..8 V compatible.
Separate output power (V
DDQ
) pins are used to decouple output
noise from the internal circuits and are 1.8 V compatible.
Functional Description
Applications
The GS8161V18B(T/D)/GS8161V32B(D)/GS8161V36B(T/D) is
an 18,874,368-bit high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally developed
for Level 2 Cache applications supporting high performance
CPUs, the device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip set
support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
Parameter Synopsis
-250
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
2.5
4.0
280
330
5.5
5.5
210
240
-200
3.0
5.0
230
270
6.5
6.5
185
205
-150
3.8
6.7
185
210
7.5
7.5
170
190
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
Rev: 1.00 8/2004
1/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161V18B(T/D)/GS8161V32B(D)/GS8161V36B(T/D)
TQFP Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
NC
BW
B
A
, B
B,
B
C
, B
D
CK
GW
E
1
G
ADV
ADSP, ADSC
ZZ
TMS
TDI
TDO
TCK
FT
LBO
V
DD
V
SS
V
DDQ
Type
I
I
I/O
—
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
I
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.00 8/2004
4/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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