Ver0.1
A1 PROs
1
A1 PROs
Ai9943
Complete 10-bit , 25MHz CCD Signal Processor
General Description
The Ai9943 is a complete analog signal
processor for CCD applications. It features a
25 MHz single-channel architecture designed
to sample and condition the outputs of
interlaced and progressive scan area CCD
arrays. The signal chain for the Ai9943
consists of a correlated double sampler (CDS),
a digitally controlled variable gain amplifier
(VGA), and a black level clamp. The Ai9943
offers 10-bit ADC resolution.
The internal registers are programmed through
a 3-wire serial digital interface. Programmable
features include gain adjustment, black level
adjustment, input clock polarity, and power-
down modes. The Ai9943 operates from a
single 3 V power supply and typically
dissipates 79 mW.
Features
- 25 MSPS correlated double sampler (CDS)
- 6 dB to 40 dB 10-bit variable gain amplifier (VGA)
- Low noise optical black clamp circuit
- Preblanking function
- 10-bit, 25 MSPS A/D converter
- No missing codes guaranteed
- 3-wire serial digital interface
- 3 V single-supply operation
- Space-saving 32-lead, 5 mm
×
5 mm QFN package
Applications
- Digital still cameras
- Digital video camcorders
- PC cameras
- Portable CCD imaging devices
- CCTV cameras
Functional Block Diagram
1
Ai9943
General Specifications
(
T
MIN
to T
MAX
, AVDD = DVDD = DRVDD = 3 V, f
SAMP
= 25 MHz, unless otherwise noted)
Value
Parameter
Min
Temperature
Range
Operating
Storage
-20
-65
2.7
79
150
25
Unit
Typ
Max
+85
+150
3.6
℃
℃
Power Supply Voltage (AVDD, DVDD, DRVDD)
Power
Consumption
Normal Operation
Power-down Mode
V
mW
μW
MHz
Maximum Clock Rate
Digital Specifications
( DRVDD = DVDD = 2.7 V, C
L
= 20 pF, unless otherwise noted.)
Value
Parameter
High Level Input Voltage
Low Level Input Voltage
Symbol
Min
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
2.2
10
10
10
2.1
0.6
Unit
Typ
Max
V
V
μA
μA
pF
V
Logic
Inputs
High Level Input Current
Low Level Input Current
Input Capacitance
High Level Output Voltage
I
OH
= 2 mA
Low Level Output Voltage
I
OL
= 2 mA
Logic
Outputs
0.5
V
2
Ai9943
System Specifications
(T
MIN
to T
MAX
, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted
)
Parameter
CDS
Maximum Input Range
before Saturation (*1)
Allowable CCD Reset Transient
Maximum CCD Black Pixel Amplitude
Value
Min
Typ
Max
Unit
Conditions
1.0
500
100
1024
Guaranteed
Vp-p
mV
mV
steps
See “Variable
Gain Amplifier”
section
for VGA gain equation and the VGA
gain curve.
See input waveform in footnote
Variable Gain Amplifier (VGA)
Gain Control Resolution
Gain Monotonicity
Minimum gain
Gain Range
Maximum gain
40
41.5
256
0
63.75
dB
steps
LSB
Measured at ADC output
Maximum clamp level
LSB
5.3
dB
Black Level Clamp
Clamp Level Resolution
Minimum clamp level
Clamp Level
A/D Converter
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Data Output Coding
Full Scale Input Voltage
10
Bits
±
0.3
Guaranteed
Straight binary
2.0
2.0
1.0
LSB
V
V
V
Specifications include entire signal
chain.
Voltage Reference
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
System Performance
Gain Range
Gain Accuracy
Peak Nonlinearity 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
(*1):
Low gain (VGA code = 0)
Maximum gain
(VGA code = 1023)
5.3
40
41.5
dB
dB
dB
%
LSB rms
dB
±
1
0.1
0.3
50
12 dB gain applied
AC grounded input, 6dB gain applied
Measured with step change on supply
3
Ai9943
Timing Specifications
( CL = 20 pF, f
SAMP
= 25 MHz. See CCD-mode timing in the section “CCD-mode Timing”)
Parameter
Sample Clocks
DATACLK, SHP, SHD Clock Period
DATACLK High / Low Pulse Width
SHP Pulse Width
SHD Pulse Width
CLPOB Pulse Width (*1)
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
Data Outputs
Output Delay
Pipeline Delay
Serial Interface
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
Symbol
Value
Min
40
16
20
10
10
2
16
20
10
20
3.0
9.5
9
Typ
Max
Unit
t
CONV
t
ADC
t
SHP
t
SHD
t
COB
t
S1
t
S2
t
ID
t
OD
ns
ns
ns
ns
Pixels
ns
ns
ns
ns
Cycles
MHz
ns
ns
ns
ns
t
SCLK
t
LS
t
LH
t
DS
t
DH
10
10
10
10
10
(*1):
Minimum CLPOB pulse width is for functional operation only. Wider pulses are recommended to obtain
low noise clamp performance.
4
Ai9943
Absolute Maximum Ratings
Parameter (with respect to)
Min
AVDD (AVSS)
Supply
Voltage
DVDD (DVSS)
DRVDD (DRVSS)
SHD, SHP, DATACLK (DVSS)
CLPOB, PBLK (DVSS)
Input Voltage
SCK, SL, SDATA (DVSS)
CCDIN (AVSS)
Output
Voltage
D0 - D9 (DRVSS)
REFT, REFTB (AVSS)
- 0.3
- 0.3
- 0.3
- 0.3
DVDD + 0.3
AVDD + 0.3
DRVDD + 0.3
AVDD + 0.3
V
V
V
V
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
Rating
Typ
Max
+ 3.9
+ 3.9
+ 3.9
DVDD + 0.3
DVDD + 0.3
Unit
V
V
V
V
V
NOTE :
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage
to the device. This is a stress rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
5
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