VPX 3225D, VPX 3224D
Contents, continued
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Section
4.
4.1.
4.2.
4.2.1.
4.2.2.
4.2.3.
4.2.4.
4.3.
4.3.1.
4.3.2.
4.3.3.
4.3.4.
4.3.5.
4.3.6.
4.3.7.
4.3.8.
4.3.10.
4.3.10.1.
4.3.10.2.
5.
5.1.
5.2.
5.3.
5.4.
5.5.
5.7.
5.7.1.
6.
6.1.
6.1.1.
6.1.2.
6.1.2.1.
7.
7.1.
7.2.
7.3.
7.3.1.
7.3.2.
7.3.3.
7.3.4.
7.3.5.
7.3.6.
7.4.
7.5.
8.
Title
PRELIMINARY DATA SHEET
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Recommended Analog Video Input Conditions
Recommended I
2
C Conditions
Recommended Digital Inputs Levels of RES, OE, TCK, TMS, TDI
Recommended Crystal Characteristics
Characteristics
Current Consumption
Characteristics, Reset
XTAL Input Characteristics
Characteristics, Analog Front-End and ADCs
Characteristics, Control Bus Interface
Characteristics, JTAG Interface (Test Access Port TAP)
Characteristics, Digital Inputs/Outputs
Digital Video Interface
Characteristics, TTL Output Driver
TTL Output Driver Type A
TTL Output Driver Type B
Timing Diagrams
Power-up Sequence
Default Wake-up Selection
I
2
C Bus Timing Diagram
Output Enable by Pin OE
Timing of the Test Access Port TAP
Timing Diagram of the Digital Video Interface
Characteristics, Clock Signals
Control and Status Registers
Overview
Description of I
2
C Control and Status Registers
Description of FP Control and Status Registers
TV Standard Coding
Application Notes
Differences between VPX 3220A and VPX 322xD
Impact to Signal to Noise Ratio
Control Interface
Symbols
Write Data into I
2
C Register
Read Data from I
2
C Register
Write Data into FP Register
Read Data from FP Register
Sample Control Code
Xtal Supplier
Typical Application
Data Sheet History
MICRONAS INTERMETALL
PRELIMINARY DATA SHEET
VPX 3225D, VPX 3224D
Text Support (VPX 3225D only)
– multistandard teletext, data slicer, intercast
WST, VPS, WSS
CAPTION (1x,2x), NABTS
Antiope
VITC
– high performance text decoding without CPU
– programmable to new standards via I
2
C
– automatic slice level adaptation
– PAL and NTSC mode
– VBI and full-field mode
– text data insertion into video stream
– simultaneous acquisition of teletext, VPS, WSS, and
caption
Miscellaneous
– 44-pin PLCC packages
– total power consumption of below 1 W
– I
2
C serial control, 2 different device addresses
– single on-chip clock generation, only one crystal need-
ed for all standards
– user programmable output pins
– power-down mode
– IEEE 1149.1 (JTAG) boundary scan interface
Video Pixel Decoder
Note: This data sheet describes functions and char-
acteristics of VPX 322xD–B2.
1. Introduction
The Video Pixel Decoders VPX 3225D and VPX 3224D
are the second generation of full feature video acquisi-
tion ICs for consumer video and multimedia applica-
tions. All of the processing necessary to convert an ana-
log video signal into a digital component stream have
been integrated onto a single 44-pin IC. Moreover, the
VPX 3225D provides text slicing for intercast, teletext,
and closed caption. Both chips are pin compatible to
VPX 3220A, VPX 3216B, and VPX 3214C. Notable fea-
tures include:
Video Decoding
– multistandard color decoding:
NTSC-M, NTSC-443
PAL-BGHI, PAL-M, PAL-N, PAL-60
SECAM
S-VHS
– NTSC with Y/C comb filter
– two 8-bit video A/D converters with clamping and auto-
matic gain control (AGC)
– four analog inputs with integrated selector for:
3 composite video sources (CVBS), or
2 Y/C sources (S-VHS), or
2 composite video sources and one Y/C source.
– horizontal and vertical sync detection for all standards
Video Processing
– hue, brightness, contrast, and saturation control
– dual window cropping and scaling
– horizontal resizing between 32 and 864 pixels/line
– vertical resizing by line dropping
– high quality anti-aliasing filter
– scaling controlled peaking and coring
Video Interfacing
– YC
b
C
r
4:2:2 format
– ITU-R 601 compliant output format
– ITU-R 656 compliant output format
– BStream compliant output format
– square pixel format (640 or 768 pixel/line)
– 8-bit or 16-bit synchronous output mode
– 13.5 MHz/16-bit and 27 MHz/8-bit output rate
– VBI bypass and raw ADC data output
MICRONAS INTERMETALL
1.1. System Architecture
The block diagram (Fig. 1–1) illustrates the signal flow
through the VPX. A sampling stage performs 8-bit A/D
conversion, clamping, and AGC. The color decoder sep-
arates the luma and chroma signals, demodulates the
chroma, and filters the luminance. A sync slicer detects
the sync edge and computes the skew relative to the
sample clock. The video processing stage resizes the
YCbCr samples, adjusts the contrast and brightness,
and interpolates the chroma. The text slicer extracts
lines with text information and delivers decoded data
bytes to the video interface.
Note:
The VPX 3225D and VPX 3224D are not register
compatible with the VPX 3220A, VPX 3216B, and
VPX 3214C family.
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