64MB (x64, SR), 128MB (x64, DR)
168-PIN SDRAM UDIMM
SYNCHRONOUS
DRAM MODULE
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
168-pin, dual in-line memory module (DIMM)
PC100- and PC133- compliant
Utilizes 125 MHz and 133 MHz SDRAM components
Unbuffered
64MB (8 Meg x 64), 128MB (16 Meg x 64)
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal SDRAM banks for hiding row access/
precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
Self Refresh Mode: 64ms, 4,096-cycle refresh
(15.625µs refresh interval)
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD)
Gold edge contacts
MT8LSDT864A – 64MB
MT16LSDT1664A – 128MB
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
Figure 1: 168-Pin DIMM (MO-161)
Standard 1.375in. (34.93mm)
Low Profile 1.125in. (28.58mm)
Options
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Memory Clock/CAS Latency
7.5ns (133 MHz)/CL = 2
7.5ns (133 MHz)/CL = 3
10ns (100 MHz)/CL = 2
• PCB
Standard 1.375in. (34.93mm)
Low Profile 1.125in. (28.58mm)
NOTE:
Marking
G
Y
1
-13E
-133
-10E
See page 2 note
See page 2 note
Table 1:
Timing Parameters
SETUP
TIME
1.5
1.5
2ns
HOLD
TIME
0.8
0.8
1ns
CL = CAS (READ) latency
ACCESS TIME
MODULE
CLOCK
MARKING FREQUENCY CL = 2 CL = 3
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
5.4ns
–
9ns
–
5.4ns
7.5ns
1. Contact Micron for product availability.
Table 2:
Address Table
64MB
128MB
4K
4 (BA0, BA1)
64Mb (8 Meg x 8)
4K (A0–A11)
512 (A0–A8)
2 (S0, S2; S1, S3)
4K
4 (BA0, BA1)
64Mb (8 Meg x 8)
4K (A0–A11)
512 (A0–A8)
1 (S0, S2)
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
pdf: 09005aef812230b2, source: 09005aef81037690
SD8_16C8_16x64AG.fm - Rev. C 7/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
64MB (x64, SR), 128MB (x64, DR)
168-PIN SDRAM UDIMM
Table 3:
Part Numbers
MODULE DENSITY
64MB
64MB
64MB
64MB
64MB
64MB
128MB
128MB
128MB
128MB
128MB
128MB
CONFIGURATION
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
SYSTEM BUS SPEED
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
PART NUMBER
MT8LSDT864AG-13E_
MT8LSDT864AY-13E_
MT8LSDT864AG-133_
MT8LSDT864AY-133_
MT8LSDT864AG-10E_
MT8LSDT864AY-10E_
MT16LSDT1664AG-13E_
MT16LSDT1664AY-13E_
MT16LSDT1664AG-133_
MT16LSDT1664AY-133_
MT16LSDT1664AG-10E_
MT16LSDT1664AY-10E_
NOTE:
1. The designators for component and PCB revision are the last two characters of each part number Consult factory for cur-
rent revision codes. Example: MT16LSDT1664AG-133B1.
pdf: 09005aef812230b2, source: 09005aef81037690
SD8_16C8_16x64AG.fm - Rev. C 7/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
64MB (x64, SR), 128MB (x64, DR)
168-PIN SDRAM UDIMM
Table 4:
Pin Assignment
(168-Pin DIMM Front)
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DNU
V
SS
NC
NC
V
DD
WE#
DQMB0
DQMB1
S0#
NC
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CK0
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
V
SS
NC
S2#
DQMB2
DQMB3
NC
V
DD
NC
NC
DNU
DNU
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
CKE1
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
NC
SDA
SCL
V
DD
Table 5:
Pin Assignment
(168-Pin DIMM Back)
106 DNU
127
V
SS
148
107
V
SS
128 CKE0
149
108
NC
129
S3#
150
109
NC
130 DQMB6 151
110
V
DD
131 DQMB7
152
111 CAS# 132
NC
153
154
112 DQMB4 133
V
DD
113 DQMB5 134
NC
155
114
S1#
135
NC
156
115 RAS# 136 DNU
157
116
V
SS
137 DNU
158
117
A1
138
V
SS
159
118
A3
139 DQ48 160
119
A5
140 DQ49 161
120
A7
141 DQ50
162
121
A9
142 DQ51
163
122
BA0
143
V
DD
164
123
A11
144 DQ52
165
124
V
DD
145
NC
166
125
CK1
146
NC
167
126
NC
147
NC
168
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
DD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
DNU
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
DNU
Figure 2: 168-Pin DIMM Pin Locations
Front View
U1
U2
U3
U4
Standard
Front View
U6
U7
U8
U9
U1
U2
U3
Low-Profile
U10
U4
U6
U7
U8
U9
U10
PIN 1
PIN 41
PIN 84
PIN 1
PIN 41
PIN 84
Back View (Populated only for 1GB module)
U11
U12
U13
U14
U16
U17
U18
U19
Back View (Populated only for dual-rank module)
U11
U12
U13
U14
U16
U17
U18
U19
PIN 168
PIN125
PIN 85
PIN 168
PIN 125
PIN 85
Indicates a V
DD
pin
Indicates a V
SS
pin
pdf: 09005aef812230b2, source: 09005aef81037690
SD8_16C8_16x64AG.fm - Rev. C 7/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
64MB (x64, SR), 128MB (x64, DR)
168-PIN SDRAM UDIMM
Table 6:
Pin Descriptions
SYMBOL
RAS#, CAS#, WE#
CK0–CK3
TYPE
Input
DESCRIPTION
NOTE: Pin numbers may not correlate with symbols; refer to Pin Assignment tables page 3 for more information
PIN NUMBERS
27, 111, 115
42, 79, 125, 163
63, 128
CKE0, CKE1
30, 45, 114, 129
S0#–S3#
28, 29, 46, 47,
112, 113, 130, 131
DQMB0–DQMB7
39, 122
BA0, BA1
33, 34, 35, 36, 37, 38, 117, 118,
119, 120, 121, 123
A0–A11
83
82
SCL
SDA
165, 166, 167
2–5, 7–11, 13–17, 19, 20, 55–
58, 60, 65–67, 69–72, 74–77,
86–89, 91–95, 97–101, 103,
104, 139–142, 144, 149–151,
153–156, 158–161
SA0, SA1, SA2
DQ0–DQ63
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Input Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the
output registers.
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW)
the CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device
banks idle), ACTIVE POWER- DOWN (row ACTIVE in any
device bank) or CLOCK SUSPEND operation (burst access in
progress). CKE is synchronous except after the device enters
power- down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input
buffers, including CK, are disabled during power-down and
self refresh modes, providing low standby power.
Input Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Input Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Input Address Inputs: Provide the row address for ACTIVE
commands, and the column addres and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address input also provide the op-code
during a MODE REGISTER SET command.
Input Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used
Output to transfer addresses and data into and data out of the
presence-detect portion of the module.
Input Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Input/ Data I/O: Data bus.
Output
pdf: 09005aef812230b2, source: 09005aef81037690
SD8_16C8_16x64AG.fm - Rev. C 7/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
64MB (x64, SR), 128MB (x64, DR)
168-PIN SDRAM UDIMM
Table 6:
Pin Descriptions
SYMBOL
V
DD
TYPE
DESCRIPTION
NOTE: Pin numbers may not correlate with symbols; refer to Pin Assignment tables page 3 for more information
PIN NUMBERS
6, 18, 26, 40, 41, 49, 59, 73, 84,
90, 102, 110, 124, 133, 143,
157, 168
1, 12, 23, 32, 43, 54, 64, 68, 78,
85, 96, 107, 116, 127, 138, 148,
152, 162
21, 22, 52, 53, 105, 106 136,
137
24, 25, 31, 44, 48, 50, 51 61,
62, 80, 81, 108, 109, 126, 132,
134, 135, 145, 146, 147, 164
Supply Power Supply: +3.3V ±0.3V.
V
SS
Supply Ground.
DNU
–
NC
–
Do Not Use: These pins are not connected on this module,
but are assigned pins on other modules in this product
family.
Not Connected: These pins are not connected on this
module.
pdf: 09005aef812230b2, source: 09005aef81037690
SD8_16C8_16x64AG.fm - Rev. C 7/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
京公网安备 11010802033920号
EEWORLD
