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PRELIMINARY
CYP15G0401TB
Quad HOTLink II™ Transmitter
Features
• Quad transmitter for 195 to 1500 MBaud serial signaling
rate
— Aggregate throughput of 6 GBits/second
• Second-generation HOTLink
®
technology
• Compliant to multiple standards
— ESCON, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
— 8B/10B encoded or 10-bit unencoded data
• Selectable parity check
• Selectable input clocking options
• Synchronous LVTTL parallel interface
• Optional Phase Align Buffer in Transmit Path
• Internal phase-locked loop (PLL) with no external PLL
components
• Dual differential PECL-compatible serial outputs per
channel
—
Source matched for 50Ω transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• Compatible with
— fiber-optic modules
— copper cables
— circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Low power 1.9W @ 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb free package option available
•
0.25µ BiCMOS technology
Functional Description
The CYP15G0401TB Quad HOTLink II™ Transmitter is a
point-to-point or point-to-multipoint communications building
block allowing the transfer of data over high-speed serial links
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195-to-1500 MBaud
per serial link.
Each transmitter accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data.
Figure 1
illustrates typical connections
between independent host systems and corresponding
CYP15G0401TB and CYP15G0401RB parts.
As a second-generation HOTLink device, the CYP15G0401TB
extends the HOTLink family with enhanced levels of
integration and faster data rates, while maintaining serial-link
compatibility (data, command, and BIST) with other HOTLink
devices. The transmitters (TX) of the CYP15G0401TB Quad
HOTLink II consist of four byte-wide channels. Each channel
can accept either eight-bit data characters or pre-encoded
10-bit transmission characters. Data characters are passed
from the Transmit Input Register to an embedded 8B/10B
Encoder to improve their serial transmission characteristics.
These encoded characters are then serialized and output from
dual Positive ECL (PECL)-compatible differential trans-
mission-line drivers at a bit-rate of either 10- or 20-times the
input reference clock. The integrated 8B/10B Encoder may be
bypassed for systems that present externally encoded or
scrambled data at the parallel interface.
Serial Link
10
10
CYP15G0401TB
CYP15G0401RB
System Host
10
Serial Link
10
10
Serial Link
10
10
Backplane or
Cabled
Connections
Figure 1. HOTLink II System Connections
Cypress Semiconductor Corporation
Document #: 38-02112 Rev. **
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised February 14, 2005
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System Host
Serial Link
10
PRELIMINARY
CYP15G0401TB
The parallel input interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture.
Each transmitter contains an independent BIST pattern
generator. This BIST hardware allows at-speed testing of the
high-speed serial data paths in each transmit section, and
across the interconnecting links.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point serial links. Some applications include
interconnecting backplanes on switches, routers, servers and
video transmission systems.
CYP15G0401TB Transmitter Logic Block Diagram
TXDC[7:0]
TXCTC[1:0]
TXDA[7:0]
TXCTA[1:0]
TXDB[7:0]
TXCTB[1:0]
TXDD[7:0]
TXCTD[1:0]
x10
x10
x10
x10
Phase
Align
Buffer
Encoder
8B/10B
Phase
Align
Buffer
Encoder
8B/10B
Phase
Align
Buffer
Encoder
8B/10B
Phase
Align
Buffer
Encoder
8B/10B
Serializer
Serializer
Serializer
Serializer
TX
TX
TX
TX
OUTB1±
OUTB2±
OUTC1±
OUTC2±
Document #: 38-02112 Rev. **
OUTA1±
OUTA2±
OUTD1±
OUTD2±
Page 2 of 30
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PRELIMINARY
CYP15G0401TB
Transmit Path Block Diagram
REFCLK+
REFCLK–
TXRATE
SPDSEL
TXCLKO+
TXCLKO–
TXMODE[1:0]
TXCKSEL
TXPERA
Phase-align
Buffer
Input
Register
12
12
12
BIST LFSR
8B/10B
SCSEL
TXDA[7:0]
TXOPA
TXCTA[1:0]
8
2
2
Character-Rate Clock
BIST Enable
Latch
Transmit
Mode
4
Output
Enable
Latch
8
Shifter
Parity
Check
10
OUTA1+
OUTA1–
OUTA2+
OUTA2–
TRSTZ
Transmit PLL
Clock Multiplier
Bit-rate Clock
BISTLE
BOE[7:0]
OELE
H M L
TXCLKA
TXPERB
Phase-align
Buffer
BIST LFSR
8B/10B
Input
Register
Shifter
Parity
Check
TXDB[7:0]
TXOPB
TXCTB[1:0]
8
2
11
11
12
10
OUTB1+
OUTB1–
OUTB2+
OUTB2–
H M L
TXCLKB
TXPERC
Phase-align
Buffer
Input
Register
Shifter
Parity
Check
11
11
12
BIST LFSR
8B/10B
10
OUTC1+
OUTC1–
OUTC2+
OUTC2–
TXDC[7:0]
TXOPC
TXCTC[1:0]
8
2
H M L
TXCLKC
TXPERD
Phase-align
Buffer
BIST LFSR
8B/10B
Input
Register
Shifter
Parity
Check
TXDD[7:0]
TXOPD
TXCTD[1:0]
8
11
11
12
10
OUTD1+
OUTD1–
OUTD2+
OUTD2–
H M L
TXCLKD
TXRST
PARCTL
Document #: 38-02112 Rev. **
JTAG
Boundary
Scan
Controller
TMS
TCLK
TDI
TDO
Page 3 of 30
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PRELIMINARY
CYP15G0401TB
Pin Configuration
(Top View)
[1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
N/C
2
OUT
C1-
OUT
C1+
TMS
3
N/C
4
OUT
C2-
OUT
C2+
V
CC
5
V
CC
6
N/C
7
OUT
D1-
OUT
D1+
N/C
8
GND
9
GND
10
OUT
D2-
OUT
D2+
11
GND
12
OUT
A1-
OUT
A1+
13
GND
14
N/C
15
OUT
A2-
OUT
A2+
GND
16
V
CC
17
N/C
18
OUT
B1-
OUT
B1+
GND
19
N/C
20
OUT
B2-
OUT
B2+
TDO
V
CC
V
CC
V
CC
V
CC
GND
N/C
N/C
GND
GND
V
CC
V
CC
GND
TDI
V
CC
V
CC
PAR
CTL
V
CC
GND
BOE[7] BOE[5] BOE[3] BOE[1]
GND
TX
MODE
[0]
TX
MODE
[1]
V
CC
TX
RATE
V
CC
GND
TCLK
TRSTZ
V
CC
V
CC
V
CC
SPD
SEL
GND
BOE[6] BOE[4] BOE[2] BOE[0]
GND
GND
V
CC
GND
N/C
N/C
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
TXPER
C
TXDC
[7]
GND
TXOP
C
TXCK
SEL
GND
TXDC
[0]
TXDC
[4]
GND
N/C
BISTLE
N/C
N/C
N/C
TXDC
[1]
GND
GND
OELE
N/C
N/C
GND
GND
GND
GND
TXCTC
[1]
N/C
TXDC
[5]
N/C
TXDC
[2]
TXCTC
[0]
TXCLK
C
N/C
TXDC
[3]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
TXDC
[6]
N/C
N/C
N/C
N/C
TXDB
[6]
TXCLK
B
GND
N/C
N/C
TXCTB TXCTB
[1]
[0]
GND
GND
TXDB
[7]
GND
GND
GND
GND
GND
N/C
N/C
N/C
N/C
TXDB
[5]
TXDB
[1]
V
CC
TXDB
[4]
TXDB
[0]
V
CC
TXDB
[3]
TXOP
B
V
CC
TXDB
[2]
TXPER
B
V
CC
N/C
N/C
TXPER
D
V
CC
TXOP
D
V
CC
V
CC
V
CC
TXDD
[0]
TXDD
[3]
TXDD
[5]
TXDD
[6]
TXDD
[1]
TXDD
[4]
TXDD
[7]
TXCLK
D
TXDD
[2]
TXCTD
[0]
N/C
TXCTD
[1]
N/C
V
CC
N/C
N/C
GND
N/C
N/C
REF
CLK-
REF
CLK+
TXDA
[1]
N/C
GND
TXDA
[4]
TXDA
[3]
TXDA
[2]
TXDA
[0]
TXCTA
[0]
TXDA
[7]
TXDA
[6]
TXDA
[5]
V
CC
N/C
N/C
N/C
N/C
V
CC
N/C
N/C
GND
N/C
N/C
GND
V
CC
N/C
N/C
N/C
N/C
N/C
V
CC
N/C
N/C
GND
TXCLK TXRST TXOPA SCSEL
O-
TXCLK
O+
N/C
TXCLK TXPER
A
A
GND
V
CC
N/C
N/C
N/C
N/C
N/C
N/C
V
CC
N/C
N/C
GND
GND
V
CC
TXCTA
[1]
N/C
N/C
N/C
Note:
1. N/C = Do Not Connect
Document #: 38-02112 Rev. **
Page 4 of 30
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