PCAL9554B; PCAL9554C
Low-voltage 8-bit I
2
C-bus and SMBus low power I/O port with
interrupt, weak pull-up and Agile I/O
Rev. 4 — 19 December 2014
Product data sheet
1. General description
The PCAL9554B and PCAL9554C are a low-voltage 8-bit General Purpose Input/Output
(GPIO) expanders with interrupt and weak pull-up for I
2
C-bus/SMBus applications. The
only difference between the PCAL9554B and PCAL9554C is their I
2
C-bus fixed address,
allowing a larger number of the same device on the I
2
C-bus with no chance of address
conflicts. NXP I/O expanders provide a simple solution when additional I/Os are needed
while keeping interconnections to a minimum, for example, in ACPI power switches,
sensors, push buttons, LEDs, fan control, etc.
In addition to providing a flexible set of GPIOs, the wide V
DD
range of 1.65 V to 5.5 V
allows the PCAL9554B/PCAL9554C to interface with next-generation microprocessors
and microcontrollers where supply levels are dropping down to conserve power.
The PCAL9554B/PCAL9554C contains the PCA9554A register set of four 8-bit
Configuration, Input, Output, and Polarity Inversion registers, and additionally, the
PCAL9554B/PCAL9554C has Agile I/O, which are additional features specifically
designed to enhance the I/O. These additional features are: programmable output drive
strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt,
interrupt status register, programmable open-drain or push-pull outputs.
The PCAL9554B is a pin-for-pin replacement for the PCA9554, while the PCAL9554C
replaces the PCA9554A, however both versions power-up with all I/O interrupted masked.
This mask default allows for a board bring-up free of spurious interrupts at power-up.
The PCAL9554B/PCAL9554C open-drain interrupt (INT) output is activated when any
input state differs from its corresponding Input Port register state and is used to indicate to
the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I
2
C-bus. Thus, the PCAL9554B or
PCAL9554C can remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
Three hardware pins (A0, A1, A2) select the fixed I
2
C-bus address and allow up to eight
devices to share the same I
2
C-bus/SMBus. The PCAL9554B and PCAL9554C differ only
in their base I
2
C-bus addresses permitting a total of 16 of the same devices on the
I
2
C-bus, minimizing the chance of address conflict, even in the most complex system.
NXP Semiconductors
PCAL9554B; PCAL9554C
Low-voltage 8-bit I
2
C-bus/SMBus low power I/O port
2. Features and benefits
I
2
C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Low standby current consumption:
1.5
A
(typical at 5 V V
DD
)
1.0
A
(typical at 3.3 V V
DD
)
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
V
hys
= 0.10
V
DD
(typical)
5 V tolerant I/Os
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I
2
C-bus
Internal power-on reset
Power-up with all channels configured as inputs
No glitch on power-up
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD78, Class II
ESD protection exceeds JESD22
2000 V Human Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: TSSOP16 and HVQFN16
2.1 Agile I/O features
Pin to pin replacement for PCA9554 and PCA9554B, PCA9554A and PCA9554C with
interrupts disabled at power-up
Software backward compatible with PCA9554 and PCA9554B, PCA9554A and
PCA9554C
Output port configuration: bank selectable push-pull or open-drain output stages
Interrupt status: read-only register identifies the source of an interrupt
Bit-wise I/O programming features:
Output drive strength: four programmable drive strengths to reduce rise and fall
times in low capacitance applications
Input latch: Input Port register values changes are kept until the Input Port register
is read
Pull-up/pull-down enable: floating input or pull-up/down resistor enable
Pull-up/pull-down selection: 100 k pull-up/down resistor selection
Interrupt mask: mask prevents the generation of the interrupt when input changes
state
PCAL9554B_PCAL9554C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 19 December 2014
2 of 42
NXP Semiconductors
PCAL9554B; PCAL9554C
Low-voltage 8-bit I
2
C-bus/SMBus low power I/O port
3. Ordering information
Table 1.
Ordering information
Topside
mark
L4B
PL9554B
L4C
PL9554C
Package
Name
HVQFN16
TSSOP16
HVQFN16
TSSOP16
Description
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3
3
0.85 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3
3
0.85 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT758-1
SOT403-1
SOT758-1
SOT403-1
Type number
PCAL9554BBS
PCAL9554BPW
PCAL9554CBS
PCAL9554CPW
3.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PCAL9554BBSHP
PCAL9554BPWJ
PCAL9554CBSHP
PCAL9554CPWJ
Package
Packing method
Minimum
order
quantity
6000
2500
6000
2500
Temperature range
Type number
PCAL9554BBS
PCAL9554BPW
PCAL9554CBS
PCAL9554CPW
HVQFN16
TSSOP16
HVQFN16
TSSOP16
Reel 13” Q2/T3
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
Reel 13” Q2/T3
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
4. Block diagram
A0
A1
A2
SCL
SDA
INPUT
FILTER
I
2
C-BUS/SMBus
CONTROL
8-bit
INPUT/
OUTPUT
PORTS
write pulse
read pulse
P0
P1
P2
P3
P4
P5
P6
P7
V
DD
V
DD
POWER-ON
RESET
V
SS
PCAL9554B
PCAL9554C
LP
FILTER
002aah204
INT
Remark:
All I/Os are set to inputs at reset.
Fig 1.
Block diagram of PCAL9554B/PCAL9554C
PCAL9554B_PCAL9554C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 19 December 2014
3 of 42
NXP Semiconductors
PCAL9554B; PCAL9554C
Low-voltage 8-bit I
2
C-bus/SMBus low power I/O port
5. Pinning information
5.1 Pinning
terminal 1
index area
13 SDA
12 SCL
11 INT
10 P7
9
5
6
7
8
P6
P5
14 V
DD
P4
16 A1
1
2
3
4
P3
A0
A1
A2
P0
P1
P2
P3
V
SS
1
2
3
4
5
6
7
8
002aah205
16 V
DD
15 SDA
14 SCL
13 INT
12 P7
11 P6
10 P5
9
P4
A2
P0
P1
P2
PCAL9554BBS
PCAL9554CBS
PCAL9554BPW
PCAL9554CPW
V
SS
15 A0
002aah206
Transparent top view
Fig 2.
Pin configuration for TSSOP16
Fig 3.
Pin configuration for HVQFN16
5.2 Pin description
Table 3.
Symbol
A0
A1
A2
P0
[1]
P1
[1]
P2
[1]
P3
[1]
V
SS
P4
[1]
P5
[1]
P6
[1]
P7
[1]
INT
SCL
SDA
V
DD
[1]
[2]
Pin description
Pin
TSSOP16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HVQFN16
15
16
1
2
3
4
5
6
[2]
7
8
9
10
11
12
13
14
address input 0
address input 1
address input 2
Port P input/output 0
Port P input/output 1
Port P input/output 2
Port P input/output 3
supply ground
Port P input/output 4
Port P input/output 5
Port P input/output 6
Port P input/output 7
interrupt output (open-drain)
serial clock line
serial data line
supply voltage
Description
All I/O are configured as input at power-on.
HVQFN16 package die supply ground is connected to both the V
SS
pin and the exposed center pad. The
V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
PCAL9554B_PCAL9554C
Product data sheet
Rev. 4 — 19 December 2014
4 of 42
NXP Semiconductors
PCAL9554B; PCAL9554C
Low-voltage 8-bit I
2
C-bus/SMBus low power I/O port
6. Functional description
Refer to
Figure 1 “Block diagram of PCAL9554B/PCAL9554C”.
6.1 Device address
slave address
0
1
0
0
A2
A1
A0 R/W
0
1
slave address
1
1
A2
A1
A0 R/W
fixed
hardware
selectable
002aah207
fixed
hardware
selectable
002aah208
a. PCAL9554B address
Fig 4.
Device address
b. PCAL9554C address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCAL9554B/PCAL9554C.
Two bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in
conjunction with the lower three bits of the Command byte are used to point to the
extended features of the device (Agile I/O). This register is write only.
B7
B6
B5
B4
B3
B2
B1
B0
002aaf540
Fig 5.
Pointer register bits
PCAL9554B_PCAL9554C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 19 December 2014
5 of 42
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