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8202-FREQ1VPCNVG

Description
CMOS Output Clock Oscillator, 4MHz Min, 100MHz Max, GREEN, SMD, 4 PIN
CategoryPassive components    oscillator   
File Size159KB,2 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

8202-FREQ1VPCNVG Overview

CMOS Output Clock Oscillator, 4MHz Min, 100MHz Max, GREEN, SMD, 4 PIN

8202-FREQ1VPCNVG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Reach Compliance Codecompliant
Other featuresSTANDBY; TUBE; SUPPLY VOLTAGE 2.5V AND 1.8V ALSO POSSIBLE
maximum descent time1.9 ns
Frequency Adjustment - MechanicalNO
frequency stability400%
JESD-609 codee3
Manufacturer's serial number8202
Installation featuresSURFACE MOUNT
Maximum operating frequency100 MHz
Minimum operating frequency4 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typeCMOS
Output load4 pF
physical size2.5mm x 2.0mm x 0.6mm
longest rise time1.9 ns
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry45/55 %
Terminal surfaceMatte Tin (Sn)
CrystalFree™ Oscillator
Ultra Low Power Oscillators
8202
PRELIMINARY DATA SHEET
Features
Frequency Range:
Output Type:
Frequency Tolerance:
Supply Voltage:
Power Consumption:
Standby Current:
Standard Package:
Operating Temperature:
4 to 133 MHz
CMOS
± 400 ppm
1.8 to 3.3 V
1.9 mA
(1.8 V)
< 1 uA
5.0 x 3.2 mm
2.5 x 2.0 mm
0 to 70 °C
-20 to 70 °C
This product is rated “Green”, please contact
factory for environmental compliancy information
Specification
Parameter
Supply Voltage
Output Frequency
Frequency Stability
Supply Current
Quiescent Current
Input LOW level
Input HIGH level
Output LOW level
Output HIGH level
Rise/Fall Time
Symbol
VDD
F
OUT
F
STB
IDD
I
STBY
V
IL
V
IH
V
OL
V
OH
T
R
/T
F
1.8 V
Specifications
2.5 V
3.3 V
4 to 133 MHz
± 400 ppm
Nominal
See ordering code
Total Frequency Stability*
Conditions
2.0 mA
2.2 mA
Typical; No load condition; 25°C
1 uA
STBY# = GND
0.3 VDD (max)
At STBY# pin
0.7 VDD (min)
0.1 VDD (max)
I
OL
= - 1 mA
0.9 VDD (min)
I
OH
= 1 mA
2.75 ns
2.3 ns
1.9 ns
20% to 80% x VDD. Output load (CL) = 4 pF
45% / 55%
For frequencies < 100MHz;
SYM
Symmetry
40% / 60%
For frequencies > 100MHz;
Start-up time
T
ST
Output valid time after VDD meets the specified range & STBY# transition
100 us
Period Jitter
PJ
RMS
4 pF load; 75 MHz
17 ps
6 ps
5 ps
Cycle to Cycle Jitter
CCJ
MAX
120 ps
50 ps
40 ps
4 pF load; 75 MHz
Note: Above specifications are typical unless otherwise specified.
* Stability over temperature, supply variation, 3x reflow, load variation, aging (10 years)
1.9 mA
Package Outline and Dimensions
3.20 ±0.05
0.90 ±0.05
1.20 ±0.05
Pin #1 ID
Chamfer
0.5 x 45°
0.85 ±0.05
0.0-0.05
Typical PCB Land Pattern
2.2
5.0 x 3.2
(mm)
STBY#
5.0 x 3.2mm
VDD
2.5
4L SMD
5.00 ±0.05
2.54
GND
0.203 Ref.
OUT
1.4
1.6
Top View
2.0 ±0.05
Bottom View
0.65 ±0.05
0.75 ±0.05
Pin #1 ID
Chamfer
0.35 x 45°
Side View
1.5
0.0-0.05
0.55 ±0.05
2.5 x 2.0
(mm)
STBY#
1.8
VDD
OUT
0.8
2.5 x 2.0mm
4L SMD
2.5 ±0.05
1.225 Bsc
0.152 Ref.
GND
0.9
0.9
Top View
June 1, 2011
Bottom View
Side View
www.IDT.com
©2011 Integrated Device Technology, Inc

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