LP324N datasheet, PDF - EEWORLD Datasheet

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LP324N: DescriptionQUAD OP-AMP, 9000uV OFFSET-MAX, 0.1MHz BAND WIDTH, PDIP14, DIP-14; CategoryAnalog mixed-signal IC Amplifier circuit; File Size272KB，8 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/; Environmental Compliance

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LP324N Overview

QUAD OP-AMP, 9000uV OFFSET-MAX, 0.1MHz BAND WIDTH, PDIP14, DIP-14

LP324N Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	DIP
package instruction	DIP-14
Contacts	14
Reach Compliance Code	unknown
Amplifier type	OPERATIONAL AMPLIFIER
Maximum average bias current (IIB)	0.02 µA
Nominal Common Mode Rejection Ratio	90 dB
Maximum input offset voltage	9000 µV
JESD-30 code	R-PDIP-T14
JESD-609 code	e0
length	19.18 mm
Humidity sensitivity level	1
Negative supply voltage upper limit
Nominal Negative Supply Voltage (Vsup)
Number of functions	4
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	260
Maximum seat height	5.08 mm
Nominal slew rate	0.05 V/us
Supply voltage upper limit	32 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	BIPOLAR
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
Nominal Uniform Gain Bandwidth	100 kHz
width	7.62 mm

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Application Report

SNOA601B – September 1981 – Revised April 2013

AN-284 Single-Supply Applications of CMOS MICRODACs

.....................................................................................................................................................

ABSTRACT

CMOS data acquisition and conversion products are becoming the ideal choice for microprocessor

controlled analog systems. The use of CMOS allows the addition of more digital logic functionality on to

the same die as the analog circuitry to minimize external parts requirements. The inherently low power

consumption is also a big factor for battery operation and low heat generation in large scale systems.

Contents

Overview

.....................................................................................................................

Reference

....................................................................................................................

List of Figures

The Standard Current-Switching R-2R Ladder Network

...............................................................

Operating the Ladder “Backwards” to Serve as a Voltage-Switching Network

.....................................

The Effects of Bringing the VCC Supply and VREF Closer Together and Temperature Performance

Using the DAC in the Voltage-Switching Mode

.........................................................................

Obtaining 0V to 10V Output from a 2.5V Reference

...................................................................

A Single-Supply DAC with Level Shift and Span Adjustable Output

.................................................

Single-Supply DAC

.........................................................................................................

Easily Calibrated, Isolated 4 mA-20 mA Current Loop Controller

....................................................

Single 5V Supply, 8-Bit CMOS DAC

.....................................................................................

All trademarks are the property of their respective owners.

SNOA601B – September 1981 – Revised April 2013

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AN-284 Single-Supply Applications of CMOS MICRODACs

Overview

www.ti.com

Overview

The MICRODAC family of 8, 10 and 12-bit D to A converters all feature on-chip data latches to permit

direct interface to 8 or 16-bit data busses. These devices were designed to provide the most versatility

from an analog standpoint. By utilizing a current switching R-2R ladder network (Figure

1),

the applied

reference voltage can be either a stable DC voltage or an AC voltage within the wide range of ±10V.

However, output linearity requires that the two current output terminals be biased to 0V. This is

accomplished by using an external op amp to serve as a current-to-voltage converter. Negative feedback

via the feedback resistor included in the DAC keeps the I

OUT1

terminal at a virtual ground potential. A

drawback to this technique is that the output amplifier inverts and outputs a voltage of the opposite polarity

of the applied reference. This then requires the output amplifier to have a negative supply voltage if the

reference were positive. To operate with only a single-supply by biasing the ground pin of the DAC and

the inputs of the op amp to ½ the supply does not work, as the digital inputs are no longer TTL

compatible.

All hope is not lost, however, if single-supply operation is essential. By taking a somewhat backwards view

of the DAC ladder network, only a single positive supply is necessary. In

Figure 2

the R-2R ladder network

is used to switch voltages rather than currents.

By applying the reference to the normal current output

terminal (I

OUT1

) and grounding I

OUT2

the voltage at the reference terminal will be a fraction of the reference

voltage and a function of the applied digital input code.

There are two important considerations when using this voltage-switching approach. The applied

reference voltage must be positive since there are internal parasitic diodes from the I

OUT

terminals to

ground which would turn on if the reference were to be negative. This, of course, is of no concern with

single-supply applications. There is also a dependence of converter linearity and gain error on the voltage

difference between the DAC's V

supply and the applied reference voltage. This is a result of the voltage

drive requirement of the CMOS ladder switches. To ensure that all of the switches can turn on sufficiently

(so as not to add significant resistance to any leg of the ladder and thereby introduce additional linearity

and gain errors) an 8-bit DAC should not have a reference greater than 5V and the V

supply should be

at least 9V more positive than the reference. This would keep linearity and gain error degradation less

than 0.1%. A 10-bit DAC is a bit more stringent. For a 0.005% or less error degradation, the reference

should be less than 3 V

and V

should be 10V more positive. The typical effects of bringing V

REF

and

closer together, as well as temperature performance, are shown graphically in

Figure 3

for the 8-bit

DAC0830 series.

N = Number of bits of resolution

Figure 1. The Standard Current-Switching R-2R Ladder Network

AN-284 Single-Supply Applications of CMOS MICRODACs

SNOA601B – September 1981 – Revised April 2013

Submit Documentation Feedback

www.ti.com

Overview

Figure 5. A Single-Supply DAC with Level Shift and Span Adjustable Output

A common requirement of single-supply systems is that the outputs of signal-conditioning amplifiers must

be DC biased, typically to ½ of the V

supply, to provide maximum unclipped AC signal swing. The circuit

Figure 6

shows how this dual-input voltage-switching DAC configuration can allow the digital input code

to control the attenuation of an AC signal without significantly affecting the DC biasing level. If the voltage

at I

OUT2

is set to the DC level of the voltage at I

OUT1

, then the term in

Equation 1

which is controlled by the

digital input code, D, reduces to just the AC signal at I

OUT1

. The DC level at the output is 255/256 times the

DC level at the input.

The circuit of

Figure 7

combines the advantages of low power consumption of the CMOS MICRODACs

together with the non-interactive zero and full-scale adjustability of this voltage-switching technique. This

circuit is an isolated 4 mA-20 mA current loop controller where the DAC sets the amount of current that

flows through the loop, yet receives its own power from the very same loop.

Digital control and isolation are provided by a single optoisolator and a CMOS counter. The controlling

processor must generate a clock and keep track of the number of clock pulses issued to the circuit to

know what the loop current is at any time. On power-up the counter is reset to all zeros to give the

processor a starting point, as well as to inherently provide a calibration point. When calibrating,

potentiometer P1 would be set for the zero-code loop current of 4 mA. The processor would then issue

exactly 255 clock pulses to the opto-isolator. Potentiometer P2 can then adjust the full-scale current value

to 19.92 mA. If one more clock pulse is issued, the DAC input code returns to all zeros and the previously

set value of 4 mA will flow, as this setting was unaffected by the full-scale adjustment.

Single-Supply DAC where the Digital Input Word Affects the Attenuation of an AC Signal without Significantly Altering

its DC Biasing Level

Figure 6. Single-Supply DAC

SNOA601B – September 1981 – Revised April 2013

Submit Documentation Feedback

AN-284 Single-Supply Applications of CMOS MICRODACs

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