A29800 Series
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Document Title
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No.
0.0
0.1
1.0
1.1
1.2
1.3
1.4
1.5
1.6
History
Initial issue
Error Correction:
P.10: Autoselect Command Sequence (line 15), XX11h
→
XX03h
Final version release
Add Pb-Free package type for -70 grade
Add -70I series products
Modify symbol “L” outline dimensions in TSOP 48L package
Update -70I series product working temperature range: read -40°C
to +85°C, erase & program 0°C to +85°C
Error correction: Modify Figure 3. Erase Operation
Modify the latency time of erase suspend from 20us to 30us.
Error correction: Modify the way to check write operation status by
either
OE
or
CE
to by
OE
and
CE
Issue Date
May 4, 2001
December 24, 2002
October 7, 2003
July 15, 2004
January 24, 2007
November 13, 2007
February 26, 2009
April 28, 2009
December 01, 2009
Remark
Preliminary
Final
1.7
Error correction: Delete t
WPH
Max. 50μs
December 21, 2009
(December, 2009, Version 1.7)
AMIC Technology, Corp.
A29800 Series
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
5.0V
±
10% for read and write operations
Access times:
- 55/70/90 (max.)
Current:
- 28mA read current (word mode)
- 20 mA typical active read current (byte mode)
- 30 mA typical program/erase current
- 1
μA
typical CMOS standby
Flexible sector architecture
-
16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors
-
8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors
-
Any combination of sectors can be erased
-
Supports full chip erase
-
Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that sector
Extended read operating temperature range: -40°C ~ +85°C
for – I series
Extended erase and program temperature range: 0°C ~
+85°C for – I series
Top or bottom boot block configurations available
Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies bytes at specified addresses
Typical 100,000 program/erase cycles per sector
20-year data retention at 125°C
- Reliable operation for the life of the system
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply
Flash memory standard
-
Superior inadvertent write protection
Data
Polling and toggle bits
-
Provides a software method of detecting completion of
program or erase operations
Erase Suspend/Erase Resume
-
Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
Hardware reset pin (
RESET
)
-
Hardware method to reset the device to reading array
data
Package options
-
44-pin SOP or 48-pin TSOP (I)
-
All Pb-free (Lead-free) products are RoHS compliant
General Description
The A29800 is a 5.0 volt only Flash memory organized as
1048,576 bytes of 8 bits or 524,288 words of 16 bits each. The
A29800 offers the
RESET
function. The 1024 Kbytes of data
are further divided into nineteen sectors for flexible sector
erase capability. The 8 bits of data appear on I/O
0
- I/O
7
while
the addresses are input on A1 to A18; the 16 bits of data
appear on I/O
0
~I/O
15
. The A29800 is offered in 44-pin SOP
and 48-Pin TSOP packages. This device is designed to be
programmed in-system with the standard system 5.0 volt VCC
supply. Additional 12.0 volt VPP is not required for in-system
write or erase operations. However, the A29800 can also be
programmed in standard EPROM programmers.
The A29800 has the first toggle bit, I/O
6
, which indicates
whether an Embedded Program or Erase is in progress, or it is
in the Erase Suspend. Besides the I/O
6
toggle bit, the A29800
has a second toggle bit, I/O
2
, to indicate whether the
addressed sector is being selected for erase. The A29800 also
offers the ability to program in the Erase Suspend mode. The
standard A29800 offers access times of 55, 70 and 90 ns,
allowing high-speed microprocessors to operate without wait
states. To eliminate bus contention the device has separate
chip enable (
CE
), write enable (
WE
) and output enable
(
OE
) controls.
The device requires only a single 5.0 volt power supply for
both read and write functions.
Internally generated and regulated voltages are provided for
the program and erase operations.
The A29800 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands
are written to the command register using standard
microprocessor write timings. Register contents serve as input
to an internal state-machine that controls the erase and
programming circuitry.
Write cycles also internally latch addresses and data needed
for the programming and erase operations. Reading data out
of the device is similar to reading from other Flash or EPROM
devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed) before
executing the erase operation.
During erase, the device automatically times the erase pulse
widths and verifies proper erase margin.
(December, 2009, Version 1.7)
1
AMIC Technology, Corp.
A29800 Series
The host system can detect whether a program or erase
operation is complete by reading the I/O
7
(
Data
Polling) and
I/O
6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The A29800 is fully erased when shipped
from the factory.
The hardware sector protection feature disables operations for
both program and erase in any combination of the sectors
of memory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any other sector that is not selected for erasure. True
background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
The hardware
RESET
pin terminates any operation in
progress and resets the internal state machine to reading
array data.
Pin Configurations
SOP
TSOP (I)
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
I/O
0
I/O
8
I/O
1
I/O
9
I/O
2
I/O
10
I/O
3
I/O
11
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
I/O
11
I/O
3
I/O
10
I/O
2
I/O
9
I/O
1
I/O
8
I/O
0
OE
VSS
CE
A0
10
11
12
13
14
15
16
17
18
19
20
21
22
A29800
35
34
33
32
31
30
29
28
27
26
25
24
23
A29800V
(December, 2009, Version 1.7)
2
AMIC Technology, Corp.
A29800 Series
Block Diagram
RY/BY
VCC
VSS
I/O
0
- I/O
15
(A-1)
Sector Switches
Erase Voltage
Generator
State
Control
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
Input/Output
Buffers
RESET
WE
BYTE
Command
Register
CE
OE
STB
VCC Detector
Timer
Address Latch
Y-Decoder
Y-Gating
A0-A18
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
A0 - A18
I/O
0
- I/O
14
I/O
15
I/O
15
(A-1)
A-1
Description
Address Inputs
Data Inputs/Outputs
Data Input/Output, Word Mode
LSB Address Input, Byte Mode
Chip Enable
Write Enable
Output Enable
Hardware Reset (N/A A298001)
Selects Byte Mode or Word Mode
Ready/
BUSY
- Output
Ground
Power Supply
CE
WE
OE
RESET
BYTE
RY/
BY
VSS
VCC
(December, 2009, Version 1.7)
3
AMIC Technology, Corp.
A29800 Series
Absolute Maximum Ratings*
Ambient Operating Temperature . . . . ….. -55°C to + 125°C
Storage Temperature . . . . . . . . . . . . . . …. -65°C to + 125°C
Ground to VCC . . . . . . . . . . . . . . . . . . . . . ….. -2.0V to 7.0V
Output Voltage (Note 1) . . . . . . . . . . . . . . …... -2.0V to 7.0V
A9,
OE
&
RESET
(Note 2) . . . . . . . . . . ….. -2.0V to 12.5V
All other pins (Note 1) . . . . . . . . . . . . . . . . ….. -2.0V to 7.0V
Output Short Circuit Current (Note 3) . . . . . . ….. . . . 200mA
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device. These
are stress ratings only. Functional operation of this device at
these or any other conditions above those indicated in the
operational sections of these specification is not implied or
intended. Exposure to the absolute maximum rating
conditions for extended periods may affect device reliability.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, inputs may undershoot VSS to -2.0V
for periods of up to 20ns. Maximum DC voltage on output
and I/O pins is VCC +0.5V. During voltage transitions,
outputs may overshoot to VCC +2.0V for periods up to
20ns.
2. Minimum DC input voltage on A9 pins is -0.5V. During
voltage transitions, A9,
OE
and
RESET
may overshoot
VSS to -2.0V for periods of up to 20ns. Maximum DC input
voltage on A9 and
OE
is +12.5V which may overshoot to
13.5V for periods up to 20ns.
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
Operating Ranges
Commercial (C) Devices
Ambient Temperature (T
A
) . . . . . . . . …. .. . . . . 0°C to +70°C
Extended Range Devices
Ambient Temperature (T
A
)
For – I series (read) . . . . . . . . . . . . . . . . . . -40°C to + 85°C
For – I series (erase, program) . . . . . . . . . . . . 0°C to + 85°C
VCC Supply Voltages
VCC for
±
10% devices . . . . . . . . . . . …... . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. A29800 Device Bus Operations
Operation
CE
L
L
VCC
±
0.5 V
H
L
X
X
OE
L
H
X
X
H
X
X
WE
H
L
X
X
H
X
X
RESET
H
H
VCC
±
0.5 V
H
H
L
V
ID
A0 - A18
I/O
0
- I/O
7
I/O
8
- I/O
15
BYTE
=V
IH
Read
Write
CMOS Standby
TTL Standby
Output Disable
Hardware Reset
Temporary Sector Unprotect
(See Note)
A
IN
A
IN
X
X
X
X
A
IN
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
D
IN
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
D
IN
BYTE
=V
IL
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5V, X = Don't Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Note:
See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.
(December, 2009, Version 1.7)
4
AMIC Technology, Corp.
京公网安备 11010802033920号
EEWORLD
