These devices consist of bus transceiver circuits with 3-state D-type
flip-flops, and control circuitry arranged for multiplexed transmission of data
directly from the input bus or from the internal registers. Data on the A or B
bus will be clocked into the registers as the appropriate clock pin goes to a
high logic level. Output Enable (OE) and DIR pins are provided to control the
transceiver function. In the transceiver mode, data present at the high
impedance port may be stored in either the A or the B register or in both. The
select controls can multiplex stored and real-time (transparent mode) data.
The direction control determines which bus will receive data when the enable
OE is Active LOW. In the isolation mode (OE HIGH), A data may be stored
in the B register and/or B data may be stored in the A register.
OCTAL TRANSCEIVER/REGISTER
WITH 3-STATE OUTPUTS
FAST™ SCHOTTKY TTL
LIFETIME BUY
•
•
•
•
Independent Registers for A and B
Multiplexed Real-Time and Stored Data
Choice of True (F646) and Inverting (F648) Data Paths
3-State Outputs
PIN ASSIGNMENTS
VCC CPBA SBA OE
24
23
22
21
B0
20
B1
19
B2
18
B3
17
B4
16
B5
15
B6
14
B7
13
24
1
J SUFFIX
CERAMIC
CASE 758-01
F646
24
1
1
2
3
CPAB SAB DIR
4
A0
5
A1
B0
20
6
A2
B1
19
7
A3
B2
18
8
A4
B3
17
9
A5
B4
16
10
A6
B5
15
11 12
A7 GND
B6
14
B7
13
24
1
VCC CPBA SBA OE
24
23
22
21
DW SUFFIX
SOIC
CASE 751E-03
F648
ORDERING INFORMATION
MC54FXXXJ
Ceramic
MC74FXXXN
Plastic
MC74FXXXDW SOIC
1
2
3
CPAB SAB DIR
4
4
A0
5
5
A1
6
6
A2
7
8
7
A3
9
8
A4
10
9
A5
11
A7
10
A6
11 12
A7 GND
4
5
6
7
8
9
10
11
A7
LOGIC SYMBOLS
1
2
3
23
22
21
A A1 A2
CPAB 0
SAB
DIR
CPBA
SBA
OE B0 B1 B2
20
19
18
A3 A4
A5 A6
F646
B3 B4
17
16
B5 B6 B7
15
14
13
1
2
3
23
22
21
A A1 A2
CPAB 0
SAB
DIR
CPBA
SBA
OE B0 B1 B2
20
19
18
A3 A4
A5 A6
F648
B3 B4
17
16
B5 B6 B7
15
14
13
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
LAST ORDER 31/03/99
N SUFFIX
PLASTIC
CASE 724-03
LAST SHIP 30/09/99
MC54/74F646
MC54/74F648
MC54/74F646
•
MC54/74F648
Inputs
OE bar
H
H
H
H
L
L
L
L
L
L
L
L
DIR
X
X
X
X
H
H
H
H
L
L
L
L
CPAB
H or L
↑
X
↑
X
↑
H or L
↑
X
X
X
X
CPBA
H or L
X
↑
↑
X
X
X
X
X
↑
H or L
↑
SAB
X
X
X
X
L
L
H
H
X
X
X
X
SBA
X
X
X
X
X
X
X
X
L
L
H
H
Data I/O*
Operation/Function
A0–A7
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
B0–B7
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Isolation
Store An Data in A Register
Store Bn Data in B Register
Store An/Bn Data in A/B Register
An to Bn — Real Time (Transparent Mode)
Store An Data in A Register
A Register to Bn (Stored Mode)
Clock An Data to Bn and into A Register
Bn to An — Real Time (Transparent Mode)
Store Bn Data in B Register
B Register to An (Stored Mode)
Clock An Data to Bn and into B Register
LIFETIME BUY
*The data output function may be enabled or disabled by various signals at the OE bar and DIR inputs. Data input functions are always enabled; i.e., data at the
*bus
pins will be stored on every low-to-high transition of the appropriate clock inputs.
H = HIGH voltage level
L = LOW voltage level
X = Don’t Care
↑
= Low-to-High transition
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Parameter
DC Supply Voltage
Operating Ambient Temperature Range
Output Current
High
Output Current
Low
54, 74
54
74
54
74
54
74
Min
4.5
–55
0
—
—
—
—
Typ
5.0
25
25
—
—
—
—
Max
5.5
125
70
–12
–15
48
64
Unit
V
mA
mA
LAST ORDER 31/03/99
°C
LAST SHIP 30/09/99
FUNCTION TABLE
MC54/74F646
•
MC54/74F648
OE
DIR
CPBA
SBA
SAB
CPAB
LIFETIME BUY
1 OF 8 CHANNELS
C0
A0
D0
B0
D0
C0
TO 7 OTHER CHANNELS
LAST ORDER 31/03/99
LAST SHIP 30/09/99
LOGIC DIAGRAM
F646
MC54/74F646
•
MC54/74F648
OE
DIR
CPBA
SBA
SAB
CPAB
LIFETIME BUY
1 OF 8 CHANNELS
C0
A0
D0
B0
D0
C0
TO 7 OTHER CHANNELS
LAST ORDER 31/03/99
LAST SHIP 30/09/99
LOGIC DIAGRAM
F648
MC54/74F646
•
MC54/74F648
Limits
Symbol
VIH
VIL
VIK
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
54/74
74
VOH
Output HIGH Voltage
O
V l
An, Bn
54
74
Parameter
Min
2.0
—
—
2.4
2.7
2.0
2.0
—
—
—
—
—
—
—
—
–100
ICCH
P
l Current
Power S
Supply C
ICCL
ICCZ
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
0.8
–1.2
—
—
—
—
0.55
0.55
20
100
1.0
–600
70
–650
–225
135
150
150
mA
Unit
V
V
V
V
V
V
V
V
V
µA
µA
mA
µA
µA
µA
mA
Test Conditions
(Note 1)
Guaranteed as a HIGH Signal
Guaranteed as a LOW Signal
VCC = MIN, IIN = –18 mA
IOH = –3.0 mA
IOH = –3.0 mA
IOH = –12.0 mA
IOH = –15.0 mA
IOL = 48 mA
IOL = 64 mA
VCC = 4.5 V
VCC = 4.75 V
VCC = 4.5 V
VCC = 4.5 V
VCC = MIN
VCC = MIN
LIFETIME BUY
54
Output LOW Voltage
An, Bn
74
Non I/O Pins
Input HIGH C
I
Current
Non I/O Pins
I/O (Aa, Bn)
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short Circuit Current (Note 2)
Non I/O Pins
I/O (An, Bn)
I/O (An, Bn)
VOL
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 5.5 V
VCC = MAX, VIN = 0.5 V
VCC = MAX
VOUT = 2.7 V
IIH
IIL
IIH + IOZH
IIL + IOZL
IOS
VCC = MAX, VOUT = 0.5 V
VCC = MAX, VOUT = GND
Vout = HIGH
Vout = LOW
Vout = HIGH Z
VCC = MAX
ICC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
LAST ORDER 31/03/99
LAST SHIP 30/09/99
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
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