Datasheet
| Rev. 1.0 | 2013
MEM5116D2DA
5 12 M b i t ( 3 2 M x 1 6 ) D o u b l e - D a t e- R a t e - T w o S D R A M
DDR2 SDRAM
1
MEM5116D2DABG
Revision History: Rev. 1.0, 2013-03
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2
MEM5116D2DABG
1 Overview
This chapter gives an overview of the 512 Mbit Double-Data-Rate-Two SDRAM product family and describes its
main characteristics.
1.1 Features
The 512 Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• 1.8 V
±
0.1 V Power Supply
• Off-Chip-Driver impedance adjustment (OCD) and
1.8 V
±
0.1 V (SSTL_18) compatible I/O
On-Die-Termination (ODT) for better signal quality
• DRAM organizations with 16 data in/outputs
• Auto-Precharge operation for read and write bursts
• Double Data Rate architecture:
• Auto-Refresh, Self-Refresh and power saving Power-
– two data transfers per clock cycle
Down modes
– four internal banks for concurrent operation
• Operating temperature range
T
CASE
0° to 95° for
C
C
• Programmable CAS Latency: 3, 4, 5, 6 and 7
standard use.
• Programmable Burst Length: 4 and 8
• Operating temperature range
T
CASE
-40° to 95° for
C
C
• Differential clock inputs (CK and CK)
industrial use.
• Bi-directional, differential data strobes (DQS and DQS) are
• Average Refresh Period 7.8
µs
at a
T
CASE
lower
transmitted / received with data. Edge aligned with read
than 85 ° 3.9
µs
between 85 ° and 95 °
C,
C
C
data and center-aligned with write data.
• Programmable self refresh rate via EMRS2 setting
• DLL aligns DQ and DQS transitions with clock
• Full and reduced Strength Data-Output Drivers
• DQS can be disabled for single-ended data strobe
• 2KB page size
)
operation
• All Speed grades faster than DDR2–400 comply with
• Commands entered on each positive clock edge, data and
DDR2–400 timing specifications when run at a clock rate
data mask are referenced to both edges of DQS
of 200 MHz.
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
command and data bus efficiency
3
MEM5116D2DA
TABLE 1
Performance Table
TABLE
Data Rate
CAS-RCD-RP latencies
Max. Clock Frequency CL3
CL4
CL5
CL6
CL7
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
1
Unit
DDR2–1066
7–7–7
DDR2–800 DDR2-800 DDR2–667
5–5–5
200
266
400
400
--
12.5
12.5
45
57.5
15
6–6–6
200
266
333
400
--
12.5
12.5
45
60
17.5
5–5–5
200
266
333
--
--
15
15
45
60
18
Note
Operational Timing Relations
t
CK
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
1)2)
f
CK3
f
CK4
f
CK5
f
CK6
f
CK7
t
RCD
t
RP
--
266
533
400
533
13.125
13.125
45
58.125
15
Precharge-All (4 banks) command
period
t
RAS
t
RC
t
PREA
Performance Table
1) This
t
PREA
value is the minimum value at which this chip will be functional.
2)
Precharge-All command for an 4 bank device will equal to
t
RP
+ 1 ×
t
CK
or
t
nRP
+ 1 × nCK, depending on the speed bin,
where
t
nRP
= RU{
t
RP
/
t
CK(avg)
} and
t
RP
is the value for a single bank precharge.
1.2 Description
The 512 Mbit DDR2 DRAM is a high-speed Double-Data-
Rate- Two CMOS Synchronous DRAM device containing
536,870,912 bits and internally configured as an octal bank
DRAM.
The 512-Mbit device is organized as
8 Mbit
×16
I/O
×4
banks. These synchronous devices
achieve high speed transfer rates starting at 400 Mb/sec/pin
for general applications. See
Table 1
for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 16 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The DDR2 device operates with a 1.8 V
±
0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in 84-ball TFBGA
package.
4
MEM5116D2DA
TABLE 2
Ordering information
TA
1
2
3
Field Description
Prefix
Memory Size [Mbit]
Bit Width (Number of I/Os)
Values
MEM
25
51
04
08
16
Coding
Memphis Memory Product
256 Mbit
512 Mbit
×4
×8
× 16
DDR1
DDR2
DDR3
1.8V
1.5V
1.35V
4
Memory Type
D1
D2
D3
5
Voltage
D
E
F
6
Die Revision
A
B
1
st
Revision
2
nd
Revision
BGA Package
TSOP Package
Green Package – RoHS Compliant, Lead- and Halogen free
Leaded device ( non RoHS)
DDR2-667 5-5-5 ( 333 MHz clock)
DDR2-800 5-5-5 (400 MHz clock)
DDR2-1066 7-7-7 (533 MHz clock)
Commercial Temp. 0° – +95 ° (
T
CASE
– Case Temp.)
C
C
1) 2)
7
8
9
Package Type
Package Material
Speed Grade
B
T
G
blank
-3
-25
-18
9
Temperature Grade
Blank
I
Industrial Temp. -40° – +95 ° (
T
CASE
– Case Temp.)
3)
C
C
BLE 2
rdering Information for RoHS Compliant Products
Notes:
Notes:
1
)
T
CASE
Case Temperature is the case surface temperature on the center / top side of the DRAM. The operating temperature
range are the temperatures where all DRAM specification will be supported. Above 85°C the Auto-Refresh command interval
has to be reduced to tREFI= 3.9μs. When operating this product in the 85°C to 95°C
T
CASE
temperature range, the High
Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to 1. When the High Temperature Self Refresh is
enabled there is an increase of IDD6 by approximately 50%.
2) During operation, the DRAM case temperature must be maintained between 0 to 95°C
T
CASE
under all other specification
parameters.
3) During operation, the DRAM case temperature must be maintained between -40 to 95°C
T
CASE
under all other specification
parameters
.
5
MEM5116D2DA
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