ST72F561J4TAXS datasheet, PDF - EEWORLD Datasheet

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ST72F561J4TAXS: Description8-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP44, 10 X 10 MM, ROHS COMPLIANT, LQFP-44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，324 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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ST72F561J4TAXS Overview

8-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP44, 10 X 10 MM, ROHS COMPLIANT, LQFP-44

ST72F561J4TAXS Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	10 X 10 MM, ROHS COMPLIANT, LQFP-44
Contacts	44
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	8
CPU series	ST72
maximum clock frequency	16 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	S-PQFP-G44
length	10 mm
Number of I/O lines	34
Number of terminals	44
On-chip program ROM width	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP44,.47SQ,32
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	1024
rom(word)	16384
ROM programmability	FLASH
Maximum seat height	1.6 mm
speed	8 MHz
Maximum slew rate	15 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST72561xx-Auto

8-bit MCU for automotive with Flash or ROM,

10-bit ADC, 5 timers, SPI, LINSCI™, active CAN

Features

■

Memories

– 16 K to 60 K High Density Flash (HDFlash)

or ROM with read-out protection capability.

In-application programming and in-circuit

programming for HDFlash devices

– 1 to 2 K RAM

– HDFlash endurance: 100 cycles, data

retention 20 years at 55 °C

Clock, reset and supply management

– Low power crystal/ceramic resonator

oscillators and bypass for external clock

– PLL for 2 x frequency multiplication

– 5 power saving modes: halt, auto wake up

from halt, active halt, wait and slow

Interrupt management

– Nested interrupt controller

– 14 interrupt vectors plus TRAP and RESET

– TLI top level interrupt (on 64-pin devices)

– Up to 21 ext. interrupt lines (on 4 vectors)

Up to 48 I/O ports

– Up to 48 multifunctional bidirectional I/Os

– Up to 36 alternate I/O functions

– Up to 6 high sink outputs

5 timers

– 16-bit timer with 2 input captures, 2 output

compares, external clock input, PWM and

pulse generator modes

– 8-bit timer with 1 or 2 input captures, 1 or 2

output compares, PWM and pulse

generator modes

– 8-bit PWM auto-reload timer with 1 or 2

input captures, 2 or 4 independent PWM

output channels, output compare and time

base interrupt, external clock with event

detector

– Main clock controller with real-time base

and clock output

– Window watchdog timer

■

LQFP32 7x7mm

LQFP44 10x10mm

LQFP64 10x10mm

LQFP64 14x14mm

■

Up to 4 communications interfaces

– SPI synchronous serial interface

– Master/ slave LINSCI™ asynchronous

serial interface

– Master only LINSCI™ asynchronous serial

interface

– CAN 2.0B active

Analog peripheral (low current coupling)

– 10-bit A/D converter with up to 16 inputs

– Up to 9 robust ports (low current coupling)

Instruction set

– 8-bit data manipulation

– 63 basic instructions, 17 main addressing

modes

– 8 x 8 unsigned multiply instruction

Development tools

– Full hardware/ software development

package

Device summary

Part number

■

Table 1.

Reference

ST72561K4-Auto, ST72561K6-Auto,

ST72561K7-Auto, ST72561K9-Auto,

ST72561J4-Auto, ST72561J6-Auto,

ST72561xx- ST72561J7-Auto, ST72561J9-Auto,

Auto

ST72561R4-Auto, ST72561R6-Auto,

ST72561R7-Auto, ST72561R9-Auto,

ST72561AR4-Auto, ST72561AR6-Auto,

ST72561AR7-Auto, ST72561AR9-Auto

January 2011

Doc ID 12370 Rev 8

1/324

www.st.com

Contents

ST72561-Auto

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.3.1

Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.1

4.2

4.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.1

5.2

5.3

5.4

5.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.5.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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ST72561-Auto

5.5.2

5.5.3

5.5.4

5.5.5

Contents

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 44

Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.6

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.6.1

5.6.2

5.6.3

5.6.4

5.6.5

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1

6.2

6.3

6.4

6.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.5.1

6.5.2

CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Interrupt software priority registers (ISPRX) . . . . . . . . . . . . . . . . . . . . . 55

6.6

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.6.1

6.6.2

I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.1

7.2

7.3

7.4

7.5

7.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Auto wake-up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.6.1

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.1

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.2.1

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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Contents

8.2.2

8.2.3

ST72561-Auto

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.3

8.4

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

I/O port register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.4.1

8.4.2

8.4.3

Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Interrupt ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Pull-up input port (CANTX requirement) . . . . . . . . . . . . . . . . . . . . . . . . 79

8.5

8.6

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Using halt mode with the WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Using halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 87

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

9.10.1

9.10.2

Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Window Register (WDGWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Main clock controller with real time clock MCC/RTC . . . . . . . . . . . . . . 89

10.1

10.2

10.3

10.4

10.5

10.6

Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Real time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.6.1

MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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Contents

11.2

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.2.7

11.2.8

11.2.9

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Counter and prescaler Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Output compare and Time base interrupt . . . . . . . . . . . . . . . . . . . . . . . 96

External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 96

Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

11.3

16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

12.1

12.2

12.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

12.3.1

12.3.2

12.3.3

12.3.4

12.3.5

12.3.6

12.3.7

12.3.8

12.3.9

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.4

12.5

12.6

12.7

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.7.1

12.7.2

12.7.3

12.7.4

12.7.5

12.7.6

12.7.7

Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 121

Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 122

Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 122

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Don’t worry about chip coins: Instead of envying the fish in the river, it is better to go home and build a net: In the forum, I often see some new friends feeling sad because they cannot download paid apps because they do not have Chip Coins. I just saw a post about an LCD1602 display based on 89C51 and other p...; 辛昕 51mcu

EEWORLD University: How to use GaN to design reliable, high-density power solutions: How to design reliable, high-density power solutions using GaN : https://training.eeworld.com.cn/course/4936...; hi5 Talking

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