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5T93GL04PGI8

Description
Low Skew Clock Driver, PDSO24
Categorylogic    logic   
File Size759KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

5T93GL04PGI8 Overview

Low Skew Clock Driver, PDSO24

5T93GL04PGI8 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
package instructionTSSOP, TSSOP24,.25
Reach Compliance Codenot_compliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G24
JESD-609 codee0
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)240
power supply2.5 V
Prop。Delay @ Nom-Sup2.2 ns
Certification statusNot Qualified
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
2.5V LVDS, 1:4 Glitchless Clock Buffer
IDT5T93GL04
TERABUFFER™ II
DATA SHEET
General Description
The IDT5T93GL04 2.5V differential clock buffer is a user-selectable
differential input to four LVDS outputs. The fanout from a differential
input to four LVDS outputs reduces loading on the preceding driver
and provides an efficient clock distribution network. The
IDT5T93GL04 can act as a translator from a differential HSTL,
eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be
used to translate to LVDS outputs. The redundant input capability
allows for
a
glitchless change-over from a primary clock source to a
secondary clock source up to 450MHz. Selectable inputs are
controlled by SEL. During the switchover, the output will disable low
for up to three clock cycles of the previously-selected input clock.
The outputs will remain low for up to three clock cycles of the
newly-selected clock, after which the outputs will start from the
newly-selected input. A FSEL pin has been implemented to control
the switchover in cases where a clock source is absent or is driven to
DC levels below the minimum specifications.
The IDT5T9304 outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the GL
pin. Multiple power and grounds reduce noise.
Features
Guaranteed low skew: <50ps (maximum)
Very low duty cycle distortion: <100ps (maximum
High speed propagation delay: <2.2ns (maximum)
Up to 450MHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interface
Selectable differential inputs to four LVDS outputs
Power-down mode
At power-up, FSEL should be LOW
2.5V V
DD
-40°C to 85°C ambient operating temperature
Available in TSSOP package
Recommends IDT5T9304 if glitchless input selectionis not
required
Applications
Clock distribution
Pin Assignment
GND
PD
FSEL
V
DD
Q1
Q1
Q2
Q2
V
DD
SEL
G
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A2
A2
GND
V
DD
Q3
Q3
Q4
Q4
V
DD
GL
A1
A1
24-Lead TSSOP
4.4mm x 7.8mm x 1.0mm package body
G Package
Top View
IDT5T93GL04 REVISION A OCTOBER 30, 2009
1
©2009 Integrated Device Technology, Inc.

5T93GL04PGI8 Related Products

5T93GL04PGI8 5T93GL04PGI
Description Low Skew Clock Driver, PDSO24 Low Skew Clock Driver, 5T Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, TSSOP-24
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
package instruction TSSOP, TSSOP24,.25 TSSOP, TSSOP24,.25
Reach Compliance Code not_compliant not_compliant
ECCN code EAR99 EAR99
JESD-30 code R-PDSO-G24 R-PDSO-G24
JESD-609 code e0 e0
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Humidity sensitivity level 1 1
Number of terminals 24 24
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP24,.25 TSSOP24,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 240 240
power supply 2.5 V 2.5 V
Prop。Delay @ Nom-Sup 2.2 ns 2.2 ns
Certification status Not Qualified Not Qualified
Nominal supply voltage (Vsup) 2.5 V 2.5 V
surface mount YES YES
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15)
Terminal form GULL WING GULL WING
Terminal pitch 0.635 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
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