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UPA2715GR

Description
Power Field-Effect Transistor, 18A I(D), 30V, 0.008ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, SOP-8
CategoryDiscrete semiconductor    The transistor   
File Size44KB,3 Pages
ManufacturerNEC Electronics
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UPA2715GR Overview

Power Field-Effect Transistor, 18A I(D), 30V, 0.008ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, SOP-8

UPA2715GR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerNEC Electronics
Parts packaging codeSOT
package instructionSMALL OUTLINE, R-PDSO-G8
Contacts8
Reach Compliance Codecompliant
ECCN codeEAR99
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage30 V
Maximum drain current (ID)18 A
Maximum drain-source on-resistance0.008 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G8
JESD-609 codee0
Number of components1
Number of terminals8
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeP-CHANNEL
Maximum pulsed drain current (IDM)150 A
Certification statusNot Qualified
surface mountYES
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
PRELIMINARY PRODUCT INFORMATION
MOS FIELD EFFECT TRANSISTOR
µ
PA2715GR
SWITCHING
P-CHANNEL POWER MOS FET
DESCRIPTION
The
µ
PA2715GR is P-Channel MOS Field Effect Transistor
designed for power management applications of notebook
computers and Li-ion battery protection circuit.
PACKAGE DRAWING (Unit: mm)
8
5
1, 2, 3
: Source
4
: Gate
5, 6, 7, 8 : Drain
FEATURES
Low on-state resistance
R
DS(on)1
= 4.5 mΩ MAX. (V
GS
= –10 V, I
D
= –9.0 A)
R
DS(on)2
= 8.0 mΩ MAX. (V
GS
= –4.5 V, I
D
= –9.0 A)
Low C
iss
: C
iss
= 5700 pF TYP.
Built-in gate protection diode
Small and surface mount package (Power SOP8)
1
4
5.37 MAX.
+0.10
–0.05
6.0 ±0.3
4.4
0.8
1.8 MAX.
1.44
0.15
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power SOP8
0.05 MIN.
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
µ
PA2715GR
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
Note3
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T1
P
T2
T
ch
T
stg
–30
m20
m18
m150
2
2
150
–55 to + 150
T.B.D.
T.B.D.
Note5
Note5
V
V
A
A
W
W
°C
°C
A
mJ
Gate
Protection
Diode
Source
Gate
Drain
EQUIVALENT CIRCUIT
Total Power Dissipation
Total Power Dissipation
Channel Temperature
Storage Temperature
Body
Diode
Single Avalanche Current
Single Avalanche Energy
Notes 1.
2.
3.
4.
5.
Note4
Note4
I
AS
E
AS
PW
10
µ
s, Duty Cycle
1%
Mounted on ceramic substrate of 1200 mm
2
x 2.2 mm
Mounted on a glass epoxy board of 1 inch x 1 inch x 0.8 mm, PW = 10 sec
Starting T
ch
= 25°C, V
DD
= –15 V, R
G
= 25
Ω,
L = 100
µ
H, V
GS
= –20
0 V
T.B.D.: To be determined.
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are availabe in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G16826EJ2V0PM00 (2nd edition)
Date Published November 2003 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2003

UPA2715GR Related Products

UPA2715GR
Description Power Field-Effect Transistor, 18A I(D), 30V, 0.008ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, SOP-8
Is it Rohs certified? incompatible
Maker NEC Electronics
Parts packaging code SOT
package instruction SMALL OUTLINE, R-PDSO-G8
Contacts 8
Reach Compliance Code compliant
ECCN code EAR99
Configuration SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 30 V
Maximum drain current (ID) 18 A
Maximum drain-source on-resistance 0.008 Ω
FET technology METAL-OXIDE SEMICONDUCTOR
JESD-30 code R-PDSO-G8
JESD-609 code e0
Number of components 1
Number of terminals 8
Operating mode ENHANCEMENT MODE
Package body material PLASTIC/EPOXY
Package shape RECTANGULAR
Package form SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED
Polarity/channel type P-CHANNEL
Maximum pulsed drain current (IDM) 150 A
Certification status Not Qualified
surface mount YES
Terminal surface TIN LEAD
Terminal form GULL WING
Terminal location DUAL
Maximum time at peak reflow temperature NOT SPECIFIED
transistor applications SWITCHING
Transistor component materials SILICON
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