LXT980/980A Dual-Speed, 5-Port Fast
Ethernet Repeater
Datasheet
General Description
The LXT980 is a 5-port 10/100 Class II Repeater that is fully compliant with IEEE 802.3
standards. Four ports directly support either 100BASE-TX/10BASE-T copper media or
100BASE-FX fiber media via pseudo-ECL (PECL) interfaces. The fifth port, a 10 or 100 Mbps
Media Independent Interface (MII), connects to Media Access Controllers (MACs) for bridge/
switch applications. At 100 Mbps, the MII can also be configured to interface to another PHY
device, such as the LXT970. This data sheet applies to all LXT980 products (LXT980,
LXT980A, and any subsequent variants), except as specifically noted.
The LXT980 provides auto-negotiation with parallel detection for the four PHY ports. These
ports can also be manually configured, either by hardware or software. The LXT980 provides
two internal repeater state machines—one operating at 10 Mbps and one at 100 Mbps. Once
configured, the LXT980 automatically connects each port to the appropriate repeater.
The LXT980 also provides two Inter-Repeater Backplanes (IRBs) for expansion — one
operating at 10 Mbps and one at 100 Mbps. Up to 240 ports can logically be combined into one
repeater using these buses. The LXT980 supports SNMP and RMON management via on-chip
32- and 64-bit counters. The counters and control information are accessible via a high-speed
Serial Management Interface (SMI). The device supports two Source Address Tracking registers
per port and a Source Address Matching Function.
Product Features
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s
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s
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Four 10/100 ports with complete twisted-
pair PHYs including integrated filters and
100BASE-FX PECL interfaces.
10/100 MII port connection to either MAC
or PHY.
Independent segments for 10 and 100 Mbps
operation.
Cascadable Inter-Repeater Backplanes
(IRBs).
Hardware assist for RMON and the
Repeater MIB.
s
s
s
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High-speed Serial Management Interface
(SMI).
Two address-tracking registers per port.
Source Address matching function.
Integrated LED drivers with user-selectable
modes.
Available in 208-pin QFP package.
Case temperature range: 0-115
°
C.
As of January 15, 2001, this document replaces the Level One document
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater.
Order Number: 249111-001
January 2001
Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Contents
1.0
2.0
Pin Assignments and Signal Descriptions
....................................................10
Functional Description
...........................................................................................20
2.1
Introduction..........................................................................................................20
2.1.1 TP/FX Port Configuration .......................................................................24
2.1.2 MII Port Configuration ............................................................................25
2.1.3 Interface Descriptions.............................................................................25
2.1.4 Repeater Operation................................................................................27
2.1.5 Management Support.............................................................................29
2.1.6 LED Drivers ............................................................................................30
Requirements ......................................................................................................30
2.2.1 Power .....................................................................................................30
2.2.2 Clock ......................................................................................................30
2.2.3 Bias Resistor ..........................................................................................30
2.2.4 Reset ......................................................................................................30
2.2.5 PROM.....................................................................................................30
2.2.6 Chip ID ...................................................................................................31
2.2.7 Management Master I/O Link .................................................................31
2.2.8 IRB Bus Pull-ups ....................................................................................31
LED Operation.....................................................................................................31
2.3.1 Blink Rates .............................................................................................32
2.3.2 Power-Up and Reset Conditions ............................................................32
2.3.3 Port LEDs ...............................................................................................32
2.3.4 Segment LEDs .......................................................................................32
2.3.5 Global LEDs ...........................................................................................33
IRB Operation......................................................................................................35
2.4.1 MAC IRB Access....................................................................................35
2.4.2 IRB Isolation ...........................................................................................35
2.4.3 MMSTRIN, MMSTROUT........................................................................36
MII Port Operation ...............................................................................................37
2.5.1 PHY Mode Operation .............................................................................38
2.5.2 MAC Mode Operation.............................................................................38
2.5.3 MII Port Timing Considerations ..............................................................39
Serial Management I/F ........................................................................................40
2.6.1 Serial Clock ............................................................................................41
2.6.2 Serial Data I/O........................................................................................41
2.6.3 Read and Write Operations....................................................................41
2.6.4 Interrupt Functions .................................................................................43
2.6.5 Address Arbitration.................................................................................44
Serial EEPROM Interface....................................................................................46
Design Recommendations ..................................................................................48
3.1.1 General Design Guidelines ....................................................................48
3.1.2 Power Supply Filtering ...........................................................................48
3.1.3 Power and Ground Plane Layout Considerations ..................................49
3.1.4 MII Terminations.....................................................................................49
2.2
2.3
2.4
2.5
2.6
2.7
3.0
Application Information
.........................................................................................48
3.1
Datasheet
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
3.2
3.1.5 The RBIAS Pin ....................................................................................... 50
3.1.6 The Twisted-Pair Interface ..................................................................... 50
3.1.7 The Fiber Interface................................................................................. 50
3.1.8 Magnetics Information............................................................................ 51
Typical Application Circuitry ................................................................................ 52
4.0
5.0
Test Specifications
.................................................................................................. 59
Register Definitions
................................................................................................ 79
5.1
Counter Registers ............................................................................................... 79
5.1.1 Port Counter Registers........................................................................... 79
5.1.2 RMON Counter Registers ...................................................................... 81
Ethernet Address Registers ................................................................................ 82
5.2.1 Port Address Tracking Registers............................................................ 82
5.2.2 Search Address Registers ..................................................................... 83
Control and Status Registers .............................................................................. 83
5.3.1 Port Link Control Register ...................................................................... 83
5.3.2 General Port Control Registers .............................................................. 84
5.3.3 Port Learn and Speed Control Registers ............................................... 85
5.3.4 Port Status Registers ............................................................................. 85
5.3.5 Interrupt Status/Mask Registers ............................................................. 86
5.3.6 MII Status Register................................................................................. 87
Configuration Registers....................................................................................... 88
5.4.1 Repeater Configuration Register............................................................ 89
Auto-Negotiation Registers ................................................................................. 92
5.2
5.3
5.4
5.5
6.0
Mechanical Specifications
................................................................................... 95
4
Datasheet
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater .................................. 9
Pin Assignments .................................................................................................10
Typical Managed Repeater Architectures ..........................................................21
Typical Unmanaged 100 Mbps Repeater Architectures .....................................21
Typical Hybrid Switch/Repeater Application .......................................................22
Typical Application Block Diagram .....................................................................23
IRB Block Diagram .............................................................................................36
MII (Port 5) Operation .........................................................................................38
MII Timing Issues ...............................................................................................40
Typical Serial Bus Architecture ..........................................................................41
Serial Management Frame Format ....................................................................43
Address Arbitration Mechanisms ........................................................................46
Serial EEPROM Interface ...................................................................................47
Optional R/W Serial EEPROM Interface ............................................................47
Managed 10/100 Repeater Stack .......................................................................52
Hybrid Switch/Repeater Application - for Balanced 10/100 Performance ..........52
Hybrid Switch/Repeater Application - Weighted Toward 100 Mbps Performance .
53
Unmanaged 100-Only Repeater Stack ..............................................................53
Power and Ground Connections ........................................................................54
Typical Fiber Port Interface ................................................................................55
Typical Twisted-Pair Port Interface and Power Supply Filtering ........................56
Typical 100 Mbps IRB Implementation ...............................................................57
Typical 10 Mbps IRB Implementation .................................................................57
Typical Serial Management Interface Connections ............................................58
Typical Reset Circuit ..........................................................................................58
100 Mbps Port-to-Port Delay Timing ..................................................................63
100BASE-TX Transmit Timing - PHY MODE MII ...............................................64
100BASE-TX Receive Timing - PHY Mode MII ..................................................65
100BASE-TX Transmit Timing - MAC Mode MII ................................................66
100BASE-TX Receive Timing - MAC Mode MII .................................................67
100BASE-FX Transmit Timing - PHY Mode MII .................................................68
100BASE-FX Receive Timing - PHY Mode MII ..................................................69
100BASE-FX Transmit Timing - MAC Mode MII ................................................70
100BASE-FX Receive Timing - MAC Mode MII .................................................71
10BASE-T Transmit Timing - PHY Mode MII .....................................................72
10BASE-T Receive Timing - PHY Mode MII ......................................................73
100 Mbps IRB Timing .........................................................................................74
10 Mbps IRB Receive Timing .............................................................................75
10 Mbps IRB Transmit Timing ............................................................................76
Serial Management Interface Timing .................................................................77
PROM Interface Timing ......................................................................................78
Package Specifications .......................................................................................95
Datasheet
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