TP/FX Port Configuration .......................................................................................................................................18
Link Establishment and TP Port Connection...................................................................................................18
Changing Port Speed On the Fly ....................................................................................................................18
MII Port Configuration ............................................................................................................................................18
Media Independent Interface (MII) ..................................................................................................................20
Serial Management Interface ..........................................................................................................................20
Management Support .............................................................................................................................................22
Configuration and Status.................................................................................................................................22
SNMP and RMON Support .............................................................................................................................22
LED Drivers ............................................................................................................................................................22
Power .....................................................................................................................................................................23
Bias Current ...........................................................................................................................................................23
Management Master I/O Link .................................................................................................................................23
IRB Bus Pull-Ups....................................................................................................................................................23
LED Operation............................................................................................................................................24
Power-Up and Reset Conditions ............................................................................................................................24
Port LEDs ...............................................................................................................................................................24
Global LEDs ...........................................................................................................................................................24
MAC IRB Access................................................................................................................................................... 28
MII Port Operation ......................................................................................................................................29
MAC Mode Operation.............................................................................................................................................30
MII Port Timing Considerations ..............................................................................................................................31
2
LXT980/980A Table of Contents
Serial Management Interface ..................................................................................................................... 32
Serial Clock ........................................................................................................................................................... 32
Serial Data I/O........................................................................................................................................................32
Read and Write Operations....................................................................................................................................32
Management Frame Format ...........................................................................................................................32
Serial EEPROM Interface ......................................................................................................................... 37
Application Information ................................................................................................................................. 38
General Design Guidelines ........................................................................................................................ 38
Power Supply Filtering......................................................................................................................... 38
Power and Ground Plane Layout Considerations ............................................................................... 37
MII Terminations .................................................................................................................................. 39
The RBIAS Pin .................................................................................................................................... 40
The Twisted-Pair Interface................................................................................................................... 39
The Fiber Interface .............................................................................................................................. 39
Magnetics Information ......................................................................................................................... 40
Test Specifications ......................................................................................................................................... 48
Absolute Maximum Ratings ....................................................................................................................... 48
Revision History ............................................................................................................................................. 91
3
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figure 1: Pin Assignments
RESET ..... 53
CLK25 ..... 54
IR10ISO ..... 55
IR100ISO ..... 56
VCC ..... 57
RECONFIG ..... 58
SRX ..... 59
STX ..... 60
SERCLK ..... 61
SER_MATCH ..... 62
MMSTROUT ..... 63
ARBOUT ..... 64
ARBSELECT ..... 65
MGR_PRES ..... 66
PROM_CLK ..... 67
PROM_CS ..... 68
PROM_DTOUT ..... 69
PROM_DTIN ..... 70
CHIPID0 ..... 71
CHIPID1 ..... 72
CHIPID2 ..... 73
AUTO_BLINK/GND
.. 74
GND ..... 75
VCC ..... 76
RPS_FAULT ..... 77
RPS_PRES ..... 78
MACACTIVE ..... 79
HOLDCOL ..... 80
IRQ ..... 81
GND ..... 82
GND ..... 83
VCC ..... 84
COL10_LED ..... 85
COL100_LED ..... 86
MGR_LED ..... 87
GND ..... 88
VCC ..... 89
ACT10_LED ..... 90
ACT100_LED ..... 91
FAULT_LED ..... 92
GND ..... 93
VCCV ..... 94
GNDV ..... 95
VCC ..... 96
N/C ..... 97
RPS_LED ..... 98
PORT5_SEL ..... 99
PORT5_SPD ..... 100
N/C ..... 101
N/C ..... 102
N/C ..... 103
GNDR ..... 104
Note:
For Pin 74 Signal Description, see Table 9 on page 13 (LXT980) and Table 11 on page 14 (LXT980A).
TPIP4......105
TPIN4......106
VCCR......107
TPOP4......108
GNDT......109
TPON4......110
VCCT......111
FIBOP4......112
FIBON4......113
SIGDET4......114
FIBIN4......115
FIBIP4......116
GNDR......117
TPIP3......118
TPIN3......119
VCCR......120
TPOP3......121
GNDT......122
TPON3......123
VCCT......124
FIBOP3......125
FIBON3......126
SIGDET3......127
FIBIN3......128
FIBIP3......129
GNDA......130
RBIAS......131
GNDR......132
TPIP2......133
TPIN2......134
VCCR......135
TPOP2......136
GNDT......137
TPON2......138
VCCT......139
FIBOP2......140
FIBON2......141
SIGDET2......142
FIBIN2......143
FIBIP2......144
GNDR......145
TPIP1......146
TPIN1......147
VCCR......148
TPOP1......149
GNDT......150
TPON1......151
VCCT......152
FIBOP1......153
FIBON1......154
SIGDET1......155
FIBIN1......156
52 ......... IR100CLK
51 ......... VCC
50 ......... GND
49 ......... IR100DAT4
48 ......... N/C
47 ......... N/C
46 ......... IR100DAT3
45 ......... IR100DAT2
44 ......... IR100DAT1
43 ......... IR100DAT0
42 ......... IR100DV
41 ......... IR100DEN
40 ......... IR100COL
39 ......... N/C
38 ......... IR100SNGL
37 ......... IR100CFSBP
36 ......... IR100CFS
35 ......... VCC
34 ......... GND
33 ......... MII_RXD3
32 ........ MII_RXD2
31 ......... N/C
30 ......... MII_RXD1
29 ......... MII_RXD0
28 ......... VCC
27 ......... GNDA
26 ......... MII_RXDV
25 ......... MII_RXCLK
24 ......... MII_RXER
23 ......... N/C
22 ......... MII_TXER
21 ......... MII_TXCLK
20 ......... MII_TXEN
19 ......... MII_TXD0
18 ......... MII_TXD1
17 ......... MII_TXD2
16 ......... MII_TXD3
15 ......... N/C
14 ......... MII_COL
13 ......... MII_CRS
12 ......... VCC
11 ......... GND
10 ......... IR10CLK
9 ........... IR10DAT
8 ........... IR10ENA
7 ........... N/C
6 ........... IR10DEN
5 ........... IR10CFSBP
4 ........... IR10COLBP
3 ........... IR10COL
2 ........... GND
1 ........... IR10CFS
(Date Code)
(Trace Code)
(Part#)
XXXX XXXX
LXT980AHC/
LXT980QC
XXXXXX
(Lot#)
208 .......LEDSEL0
207 .......LEDSEL1
206 .......VCC
205 .......VCC
204 .......VCC
203 .......VCC
202 .......GND
201 .......VCC
200 .......GND
199 .......MMSTRIN
198 .......ARBIN
197 .......CONFIG0
196 .......CONFIG1
195 .......CONFIG2
194 .......CONFIG3
193 .......CONFIG4
192 .......CONFIG5
191 .......CONFIG6
190 .......CONFIG7
189 .......PORT1_SPD0
188 .......PORT1_SPD1
187 .......PORT2_SPD0
186 .......PORT2_SPD1
185 .......PORT3_SPD0
184 .......PORT3_SPD1
183 .......PORT4_SPD0
182 .......PORT4_SPD1
181 .......PORT1_LED1
180 .......PORT1_LED2
179 .......PORT1_LED3
178 .......GND
177 .......PORT2_LED1
176 .......PORT2_LED2
175 .......PORT2_LED3
174 .......GND
173 .......PORT3_LED1
172 .......PORT3_LED2
171 .......PORT3_LED3
170 .......VCC
169 .......VCCV
168 .......GNDV
167 .......GND
166 .......PORT4_LED1
165 .......PORT4_LED2
164 .......PORT4_LED3
163 .......GND
162 .......PORT5_LED1
161 .......PORT5_LED2
160 .......PORT5_LED3
159 .......GND
158 .......GND
157 .......FIBIP1
4
LXT980/980A Pin Assignments and Signal Descriptions
Table 1: Mode Control Signal Descriptions
Pin
189
188
187
186
185
184
183
182
100
Symbol
PORT1_SPD0
PORT1_SPD1
PORT2_SPD0
PORT2_SPD1
PORT3_SPD0
PORT3_SPD1
PORT4_SPD0
PORT4_SPD1
PORT5_SPD
TTL Input,
PU
Speed Select - Port 5.
Selects operating speed of the MII (MAC) interface.
Also selects the segment on which statistics are kept.
High = 100 Mbps. Low = 10 Mbps.
(Port 5 speed of 10 Mbps is available when PHY mode is selected.)
Mode Select - Port 5.
Selects operating mode of the MII interface. Pin is
monitored at power-up and reset. Subsequent changes have no effect.
High = PHY Mode (LXT980 acts as PHY side of the MII.)
Low = MAC Mode (LXT980 acts as MAC side of the MII.)
Configuration Register Inputs.
These inputs allow the user to store
system-specific information (board type, plug-in cards, status, etc.) in the
Serial Configuration Register (address AC). This register may be read
remotely through the Serial Management Interface (SMI).
Type
1
TTL Input,
PU,
Latched on
reset
Description
Speed Select - Ports 1 through 4.
These pins set the default value of the
Port Speed Control Register for the associated port as follows:
SPD1
0
0
1
1
SPD0
0
1
0
1
Mode
Allow 10/100 auto-negotiation/parallel detection.
Force 10BASE-T.
Force 100BASE-FX.
Force 100BASE-TX.
99
PORT5_SEL
TTL Input,
PU
197
196
195
194
193
192
191
190
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
CONFIG7
TTL Input,
PD
1. NC = No Clamp. Pad will not clamp input in the absence of power.
PU = Input contains pull-up.
PD = Input contains pull-down.
TTL = Transistor-Transistor Logic.
Table 2: PHY Mode MII Interface Signal Descriptions
Pin
29
30
32
33
26
Symbol
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RXDV
Output
TTL
Receive Data Valid.
Active High signal, synchronous to MII_RXCLK, indicates
valid data on MII_RXD<3:0>.
Type
1
Output
TTL
Description
Receive Data.
The LXT980 transmits received data to the controller on these out-
puts. Data is driven on the falling edge of MII_RXCLK.
1. MII interface pins reverse direction based on PHY/MAC mode. Direction listed is for PHY mode.