Preliminary Data Sheet
August 2005
TruePHY
™
ET1011
Gigabit Ethernet Transceiver
Features
10Base-T, 100Base-TX, and 1000Base-T
gigabit Ethernet transceiver:
— 0.13 µm process
— 128-pin TQFP and 84-pin MLCC:
RGMII, GMII, MII, RTBI, and TBI interfaces to
MAC or switch
— 68-pin MLCC:
RGMII and RTBI interfaces to MAC or switch
Low power consumption:
— Typical power less than 750 mW in 1000Base-T
mode
— Advanced power management
— ACPI compliant wake-on-LAN support
Oversampling architecture to improve signal integ-
rity and SNR
Optimized, extended performance echo and NEXT
filters
All digital baseline wander correction
Digital PGA control
On-chip diagnostic support
Automatic speed negotiation
Automatic speed downshift
Single supply 3.3 V or 2.5 V operation:
— On-chip regulator controllers
— 3.3 V or 2.5 V digital I/O
— 1.0 V or 1.1 V core power supplies
— 1.8 V or 2.5 V for transformer center tap
JTAG
Introduction
Agere Systems ET1011 is a gigabit Ethernet trans-
ceiver fabricated on a single CMOS chip. Packaged
in either a 128-pin TQFP, an 84-pin MLCC, or a
68-pin MLCC, the ET1011 is built on 0.13 µm tech-
nology for low power consumption and application in
server and desktop NIC cards. It features single
power supply operation using on-chip regulator con-
trollers. The 10/100/1000Base-T device is fully com-
pliant with
IEEE
®
802.3, 802.3u, and 802.3ab
standards.
The ET1011 uses an oversampling architecture to
gather more signal energy from the communication
channel than possible with traditional architectures.
The additional signal energy or analog complexity
transfers into the digital domain. The result is an ana-
log front end that delivers robust operation, reduced
cost, and lower power consumption than traditional
architectures.
Using oversampling has allowed for the implementa-
tion of a fractionally spaced equalizer, which provides
better equalization and has greater immunity to tim-
ing jitter, resulting in better signal-to-noise ratio
(SNR) and thus improved BER. In addition,
advanced timing algorithms are used to enable oper-
ation over a wider range of cabling plants.
TruePHY
ET1011
Gigabit Ethernet Transceiver
Preliminary Data Sheet
August 2005
Table of Contents
Contents
Page
Contents
Page
Features ......................................................................1
Introduction..................................................................1
Functional Description .................................................5
Oversampling Architecture....................................5
Automatic Speed Downshift ..................................5
Transmit Functions ...............................................6
Receive Functions ................................................6
Autonegotiation .....................................................7
Carrier Sense(128-pin TQFP and 84-pin MLCC
only) .................................................................7
Link Monitor ..........................................................8
Loopback Mode ....................................................9
Digital Loopback ...................................................9
Analog Loopback ................................................10
LEDs ...................................................................11
Regulator Control ................................................11
Resetting the ET1011 .........................................11
Low-Power Modes ..............................................11
Pin Information ..........................................................12
Pin Diagram, 128-Pin TQFP ..............................12
Pin Diagram, 68-Pin MLCC ................................14
Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC,
and 68-Pin MLCC ............................................15
Hardware Interfaces ..................................................21
MAC Interface .....................................................22
Management Interface ........................................27
Configuration Interface........................................29
LEDs Interface ....................................................33
Media-Dependent Interface: Transformer
Interface...........................................................34
Clocking and Reset .............................................35
JTAG ...................................................................36
Regulator Control ................................................36
Power, Ground, and No Connect ........................37
Cable Diagnostics......................................................38
Register Description ..................................................39
Register Address Map ........................................39
Register Functions/Settings ................................40
Electrical Specifications.............................................58
Absolute Maximum Ratings ................................58
Recommended Operating Conditions .................58
Device Electrical Characteristics.........................60
Timing Specification ..................................................67
GMII 1000Base-T Transmit Timing
(128-pin TQFP only) ........................................67
GMII 1000Base-T Receive Timing
(128-pin TQFP only) ........................................68
RGMII 1000Base-T Transmit Timing ..................69
RGMII 1000Base-T Receive Timing ...................71
MII 100Base-TX Transmit Timing .......................73
MII 100Base-TX Receive Timing .......................74
2
MII 10Base-T Transmit Timing........................... 75
MII 10Base-T Receive Timing............................ 76
Serial Management Interface Timing ................. 77
Reset Timing ...................................................... 78
Clock Timing ...................................................... 79
JTAG Timing ...................................................... 80
Package Diagram, 128-Pin TQFP ............................ 81
Package Diagram, 84-Pin MLCC ............................ 82
Package Diagram, 68-Pin MLCC ............................ 83
Ordering Information................................................. 84
Related Product Documentation ....................... 84
Table
Page
Table 1. Agere Systems ET1011 Device Signals by
Interface, 128-Pin TQFP, 84-Pin
and 68-Pin MLCC ...................................... 15
Table 2. Multiplexed Signals on the ET1011.............. 20
Table 3. GMII Signal Description (1000Base-T Mode)
(128-pin TQFP and 84-pin MLCC only) ..... 22
Table 4. RGMII Signal Description
(1000Base-T Mode)................................... 23
Table 5. MII Interface (100Base-TX and 10Base-T)
(128-pin TQFP and 84-pin MLCC Only) .... 24
Table 6. Ten-Bit Interface (1000Base-T) (128-pin
TQFP and 84-pin MLCC Only) .................. 25
Table 7. RTBI Signal Description
(1000Base-T Mode) .................................. 26
Table 8. Management Frame Structure ..................... 27
Table 9. Management Interface ................................. 28
Table 10. Autonegotiation Modes .............................. 29
Table 11. Master/Slave Preference............................ 30
Table 12. MDI/MDI-X Configuration........................... 31
Table 13. Configuration Signals................................. 31
Table 14. LED ........................................................... 33
Table 15. Transformer Interface Signals.................... 34
Table 16. Clocking and Reset.................................... 35
Table 17. JTAG Test Interface ................................... 36
Table 18. Regulator Control Interface........................ 36
Table 19. Supply Voltage Combinations .................... 37
Table 20. Power, Ground, and No Connect ............... 37
Table 21. Cable Diagnostic Functions .......................38
Table 22. Register Address Map ............................... 39
Table 23. Register Type Definition............................. 39
Table 24. Control Register—Address 0 ..................... 40
Table 25. Status Register—Address 1 .......................41
Table 26. PHY Identifier Register 1—Address 2........ 42
Table 27. PHY Identifier Register 2—Address 3........ 42
Table 28. Autonegotiation Advertisement Register—
Address 4 .................................................. 43
Agere Systems Inc.
Preliminary Data Sheet
August 2005
TruePHY
ET1011
Gigabit Ethernet Transceiver
Table of Contents
(continued)
Table
Page
Table
Page
Table 29. Autonegotiation Link Partner Ability
Register—Address 5 .............................. 44
Table 30. Autonegotiation Expansion Register—
Address 6 ............................................... 45
Table 31. Autonegotiation Next Page Transmit
Register—Address 7 .............................. 45
Table 32. Link Partner Next Page Register—
Address 8 ............................................... 46
Table 33. 1000 Base-T Control Register—
Address 9 ............................................... 47
Table 34. 1000Base-T Status Register—
Address 10 ............................................. 48
Table 35. Reserved Registers—Addresses 11—14 .. 49
Table 36. Extended Status Register—Address 15 .... 49
Table 37. Reserved Registers—Addresses 16—18.. 49
Table 38. Loopback Control Register—Address 19 .. 50
Table 39. Reserved Registers—Address 20 ............. 50
Table 40. Management Interface (MI) Control
Register—Address 21 ............................ 50
Table 41. PHY Configuration Register—
Address 22 ............................................. 51
Table 42. PHY Control Register—Address 23 .......... 52
Table 43. Interrupt Mask Register—Address 24 ....... 53
Table 44. Interrupt Status Register—Address 25 ...... 54
Table 45. PHY Status Register—Address 26 ............ 55
Table 46. LED Control Register 1—Address 27........ 56
Table 47. LED Control Register 2—Address 28........ 57
Table 48. Reserved Registers—Addresses 29—31.. 57
Table 49. Absolute Maximum Ratings....................... 58
Table 50. ET1011N0 and ET1011R0 Recommended
Operating Conditions
1
............................ 58
Table 51. ET1011N1 and ET1011R1 Recommended
Operating Conditions
1
............................ 59
Table 52. Device Characteristics—3.3 V Digital I/O
Supply (DVDDIO) ................................... 60
Table 53. Device Characteristics—2.5 V Digital I/O
Supply (DVDDIO) ................................... 60
Table 54. ET1011N0 and ET1011R0 Current
Consumption GMII 1000Base-T............. 61
Table 55. ET1011N0 and ET1011R0 Current
Consumption GMII 100Base-TX ............ 61
Table 56. ET1011N0 and ET1011R0 Current
Consumption GMII 10Base-T................. 61
Table 57. ET1011N0 and ET1011R0 Current
Consumption GMII 10BASE-T Idle......... 62
Table 58. ET1011N0 and ET1011R0 Current
Consumption RGMII 1000BASE-T......... 62
Table 59. ET1011N0 and ET1011R0 Current
Consumption RGMII 100BASE-TX ........ 62
Table 60. ET1011N0 and ET1011R0 Current
Consumption RGMII 10BASE-T............. 63
Table 61. ET1011N0 and ET1011R0 Current
Consumption RGMII 10BASE-T Idle ...... 63
Table 62. ET1011N1 and ET1011R1 Current
Consumption GMII 1000Base-T............. 64
Table 63. ET1011N1 and ET1011R1 Current
Consumption GMII 100Base-TX ............ 64
Table 64. ET1011N1 and ET1011R1 Current
Consumption GMII 10Base-T................. 64
Table 65. ET1011N1 and ET1011R1 Current
Consumption GMII 10BASE-T Idle......... 65
Table 66. ET1011N1 and ET1011R1 Current
Consumption RGMII 1000BASE-T......... 65
Table 67. ET1011N1 and ET1011R1 Current
Consumption RGMII 100BASE-TX ........ 65
Table 68. ET1011N1 and ET1011R1 Current
Consumption RGMII 10BASE-T............. 66
Table 69. ET1011N1 and ET1011R1 Current
Consumption RGMII 10BASE-T Idle ...... 66
Table 70. GMII 1000Base-T Transmit Timing............ 67
Table 71. GMII 1000Base-T Receive Timing............. 68
Table 72. RGMII 1000Base-T Transmit Timing ......... 69
Table 73. RGMII 1000Base-T Transmit Timing ......... 70
Table 74 . RGMII 1000Base-T Receive Timing ......... 71
Table 75. RGMII 1000Base-T Receive Timing .......... 72
Table 76. MII 100Base-TX Transmit Timing .............. 73
Table 77. MII 100Base-TX Receive Timing ............... 74
Table 78. MII 10Base-T Transmit Timing................... 75
Table 79. MII 10Base-T Receive Timing ................... 76
Table 80. Serial Management Interface Timing ......... 77
Table 81. Reset Timing.............................................. 78
Table 82. Clock Timing .............................................. 79
Table 83. JTAG Timing .............................................. 80
Table 84. Chip Set Names and Part Numbers .......... 84
Table 85. Related Product Documentation................ 84
Agere Systems Inc.
3
TruePHY
ET1011
Gigabit Ethernet Transceiver
Preliminary Data Sheet
August 2005
Table of Contents
(continued)
Figure
Page
Figure
Page
Figure 1. ET1011 Block Diagram................................. 5
Figure 2. Loopback Functionality................................. 9
Figure 3. Digital Loopback........................................... 9
Figure 4. Replica Analog Loopback........................... 10
Figure 5. Line Driver Analog Loopback ..................... 10
Figure 6. Pin Diagram for ET1011 in 128-Pin TQFP
Package (Top View) ............................... 12
Figure 7. Pin Diagram for ET1011 in 84-Pin MLCC
Package (Top View) ............................... 13
Figure 8. Pin Diagram for ET1011 in 68-Pin MLCC
Package (Top View) ............................... 14
Figure 9. ET1011 Gigabit Ethernet Card
Block Diagram ........................................ 21
Figure 10. GMII MAC-PHY Signals ........................... 22
Figure 11. RGMII MAC-PHY Signals......................... 23
Figure 12. MII Signals................................................ 24
Figure 13. Ten-Bit Interface ....................................... 25
Figure 14. Reduced Ten-Bit Interface........................ 26
Figure 15. GMII 1000Base-T Transmit Timing .......... 67
Figure 16. GMII 1000Base-T Receive Timing ........... 68
Figure 17. RGMII 1000Base-T Transmit Timing—
Trace Delay ............................................ 69
Figure 18. RGMII 1000Base-T Transmit Timing—
Internal Delay ......................................... 70
Figure 19. RGMII 1000Base-T Receive Timing—
Trace Delay ............................................ 71
Figure 20. RGMII 1000Base-T Receive Timing—
Internal Delay ......................................... 72
Figure 21. MII 100Base-TX Transmit Timing ............. 73
Figure 22. MII 100Base-TX Receive Timing.............. 74
Figure 23. MII 10Base-T Transmit Timing ................. 75
Figure 24. MII 10Base-T Receive Timing .................. 76
Figure 25. Serial Management Interface Timing........ 77
Figure 26. Reset Timing ............................................ 78
Figure 27. Clock Timing............................................. 79
Figure 28. JTAG Timing............................................. 80
4
Agere Systems Inc.
Preliminary Data Sheet
August 2005
TruePHY
ET1011
Gigabit Ethernet Transceiver
Functional Description
Agere Systems ET1011 is a gigabit Ethernet transceiver that simultaneously transmits and receives on each of the
four UTP pairs of category 5 cable (signal dimensions or channels A, B, C, and D) at 125 Msymbols/s using five-
level pulse amplitude modulation (PAM). Figure 1 is a block diagram of its basic configuration.
GTX_CLK
TX_CLK
TXD[7:0]
TX_ER
TX_EN
RX_CLK
RXD[7:0]
RX_ER
RX_DV
COL
CRS
PMA D
PMA C
PMA B
PMA A
RGMII
GMII
MII
RTBI
TBI
BLW
Correction
Gain
Control
Bias
PCS
NEXT
Cancellers
Echo
Canceller
Transmit
Shaping
DAC
Hybrid
TRD[0-3]±
Σ
FFE
ADC
PGA
RSET
Trellis
Decoder
Timing
Control
Auto-
Negotiation
Clock
Generator
LEDS
Config
PHYAD[4:0]
MDC
MDIO
MDINT_N
LEDS/
Config
JTAG/
Test
10BASE-T
Management
Interface
Clock
MI Registers
Reset
TCK
TRST_N
TMS
TDI
TDO
SYS_CLK
XTAL_1
XTAL_2
RESET_N
Figure 1. ET1011 Block Diagram
Oversampling Architecture
The ET1011 architecture uses oversampling tech-
niques to sample at two times the symbol rate. A frac-
tionally spaced feed forward equalizer (FFE) adapts to
remove intersymbol interference (ISI) and to shape the
spectrum of the received signal to maximize the (SNR)
at the trellis decoder input. The FFE equalizes the
channel to a fixed target response. Oversampling
enables the use of a fractionally spaced equalizer
(FSE) structure for the FFE, resulting in symbol rate
clocking for both the FFE and the rest of the receiver.
This provides robust operation and substantial power
savings.
Automatic Speed Downshift
Automatic speed downshift is an enhanced feature of
autonegotiation that allows the ET1011 to:
Fallback in speed, based on cabling conditions or
link partner abilities.
Operate over CAT-3 cabling (in 10Base-T mode).
Operate over two-pair CAT-5 cabling (in 100Base-TX
mode).
For speed fallback, the ET1011 first tries to autonegoti-
ate by advertising 1000Base-T capability. After a num-
ber of failed attempts to bring up the link, the ET1011
falls back to advertising 100Base-TX and restarts the
autonegotiation process. This process continues
through all speeds down to 10Base-T. At this point,
there are no lower speeds to try and so the host
enables all technologies and starts again.
PHY configuration register, address 22, bits 11and 10
enable automatic speed downshift and specifies if fall-
back to 10Base-T is allowed. PHY control register,
address 23, bits 11and 12 specify the number of failed
attempts before downshift (programmable to 1, 2, 3, or
4 attempts).
Agere Systems Inc.
5
DSP and ARM Processors
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