PC87591S-SLB128 datasheet, PDF

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PC87591S-SLB128: DescriptionRISC Microcontroller, 16-Bit, FLASH, 20MHz, CMOS, PBGA128, CSP-128; CategoryThe embedded processor and controller Microcontrollers and processors; File Size5MB，441 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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PC87591S-SLB128 Overview

RISC Microcontroller, 16-Bit, FLASH, 20MHz, CMOS, PBGA128, CSP-128

PC87591S-SLB128 Parametric

Parameter Name	Attribute value
Maker	Winbond Electronics Corporation
Parts packaging code	BGA
package instruction	TFLGA,
Contacts	128
Reach Compliance Code	unknown
ECCN code	3A991.A.2
Has ADC	YES
Address bus width	8
bit size	16
maximum clock frequency	33 MHz
DAC channel	YES
DMA channel	YES
External data bus width	8
JESD-30 code	S-PBGA-B128
length	10 mm
Number of I/O lines	62
Number of terminals	128
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TFLGA
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
ROM programmability	FLASH
Maximum seat height	1.1 mm
speed	20 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BUTT
Terminal pitch	0.5 mm
Terminal location	BOTTOM
width	10 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

PC87591S-SLB128 Preview

PC87591E, PC87591S and PC87591L LPC Mobile Embedded Controllers

PRELIMINARY

March 2002

Revision 1.06

PC87591E, PC87591S and PC87591L

LPC Mobile Embedded Controllers

General Description

The National Semiconductor

PC87591E, PC87591S and

PC87591L are highly integrated, embedded controllers with

an embedded-RISC core and integrated advanced func-

tions. These devices are targeted for a wide range of porta-

ble applications that use the Low Pin Count (LPC) interface.

The PC87591S is targeted for security applications and in-

cludes supporting hardware such as the Hardware Random

Number Generator. The PC8591L replaces the on-chip

flash with 4K of boot ROM for value solutions using shared

BIOS architecture. “PC87591x” refers to all the devices.

The PC87591x incorporates National’s CompactRISC



CR16B core (a high-performance 16-bit RISC processor),

on-chip flash (ROM for the PC87591L) and RAM memories,

system support functions and a Bus Interface Unit (BIU) that

directly interfaces with optional external memory (such as

flash) and I/O devices.

System support functions include: WATCHDOG and other

timers, interrupt control, general-purpose I/O (GPIO) with

internal keyboard matrix scanning, PS/2

Interface,

ACCESS.bus

interface, high accuracy analog-to-digital

(ADC) and digital-to-analog converters (DAC) for battery

charging, system control, system health monitoring and an-

alog controls.

The PC87591x interfaces with the host via an LPC interface

that provides the host with access to the Keyboard and em-

bedded controller interface channels, integrated functions,

Real-Time Clock (RTC), BIOS firmware and security func-

tions.

Like members of National’s SuperI/O family, the PC87591x

is PC01 and ACPI compliant.

Outstanding Features

Host interface, based on Intel’s

LPC Interface Speciﬁ-

cation Revision 1.0,

September 29th, 1997

PC01 Rev 1.0, and ACPI 2.0 compliant

16-bit RISC core, with 2 Mbyte address space, and

running at up to 20 MHz

Software and Hardware controlled clock throttling

Shared BIOS ﬂash memory (internal and/or external)

Y2K-compliant RTC

84/117 GPIO ports (for 128-pin/176-pin packages)

with a variety of wake-up events

Extremely low current consumption in Idle mode

JTAG-based debugger interface

128-pin and 176-pin options, in LQFP and CSP pack-

ages (PC87591L is 176-pin only)

Block Diagram

LPC

I/F

Serial

IRQ

SMI

Reset &

Config

CR16B Core

Processing

Unit

DMA

Host

Controlled

Functions

LPC Bus I/F

Core Bus

I/F Functions

CR Access

Bridge

Shared mem.

+ Security

Memory

Bus

Adapter

RAM

FLASH or ROM

BIU

Internal Bus

Peripheral Bus

KBC + PM

Host I/F

HFCG

KBSCAN +

ACM

ACB

(X2)

Peripherals

Timer +

WDG

MFT16

(X2)

MSWC

ICU

GPIO

ADC

USART

PMC

CLK

MIWU

Debugger

I/F

PS/2

I/F

PWM

DAC

RTC

JTAG

External

Memory + I/O

32.768 KHz

National Semiconductor is a registered trademark of National Semiconductor Corporation. All other brand or product names are trademarks or registered trademarks of their respective holders.

www.national.com

PC87591E/S/L

Features

(Continued)

Device-Speciﬁc Information

The following table compares features for the devices in the PC87591x family. The features listed below are a superset of

the PC87591x family.

Function

Flash Size

ROM Size

RAM Size

General-Purpose Input/Output Ports (GPIO)

Shared BIOS

RNG

Memory Protection

PC87591E

128-Pin

64K

–

PC87591E

176-Pin

64K

–

YES

PC87591S

128-Pin

128K

–

YES

PC87591S

176-Pin

128K

–

YES

PC87591L

176-Pin

–

YES

Features

Processing Unit

—

CompactRISC CR16B 16-bit embedded RISC pro-

cessor core (the “core”)

—

2 Mbyte address space

Internal Memory

—

Up to 128 Kbytes of on-chip ﬂash memory (4 Kbytes

of ROM in the PC87591L)

—

Supports BIOS (ﬂash) memory sharing with PC host

—

On-chip ﬂash is ﬁeld upgradable by host, CR16B,

parallel interface or JTAG

—

Boot blocks for both CR16B and Host Code

—

Memory contents protection and security

—

Hardware-protected boot zone with block protection

circuit

—

2K (PC87591E/L) or 4K of on-chip RAM (PC87591S)

—

All memory types can hold both code and data

Expansion Memory (Optional in 176-pin package)

—

Up to 1 Mbyte of additional code and data

—

Supports BIOS (ﬂash) memory sharing with PC host

—

Supports external memory power-down mode

—

Field upgradable with ﬂash or SRAM devices

—

Supports host-controlled code download and up-

date

—

Bus Interface Unit (BIU)

❏

Three address zones for static devices (SRAM,

ROM, ﬂash, I/O)

❏

LPC System Interface

—

Synchronous cycles, up to 33 MHz bus clock

—

Serial IRQ

—

I/O and Memory read and write cycles

—

Bootable memory support

—

Bus Master read and write cycles

—

Reset input

—

Base Address (BADDR) strap to determine the base

address of the Index-Data register pair

—

LPCPD and CLKRUN support

—

FWH Transaction support

Security Function Support

—

Random Number Generator (RNG)

—

Full Random using temperature, voltage and system

noise.

—

Memory access protection

Embedded Controller System Features

Host Bus Interface (HBI)

—

Three host interface channels, typically used for the

KBC, ACPI Private or Shared EC channels

—

8042 KBC standard Interface (legacy 60

, 64

)

—

Intel 80C51SL compatible

IRQ1 and IRQ12 support

Fast Gate A20 and Fast Host Reset via ﬁrmware

PM interface port (legacy 62

, 66

)

Conﬁgurable wait states and fast-read, single-

cycle bus cycles

8- or 16-bit wide bus

—

ACPI Embedded Controller with either Shared or

Private interface

—

IRQ, SMI or SCI generation

www.national.com

Revision1.06

PC87591E/S/L

Features

(Continued)

Interrupt Control Unit (ICU)

—

31 maskable vectored interrupts (of which 26 are ex-

ternal)

—

General-purpose external interrupt inputs through

MIWU

—

Enable and pending indication for each interrupt

—

Non-maskable interrupt input

Multi-Input Wake-Up (MIWU)

—

Supports up to 32 wake-up or interrupt inputs

—

Generates wake-up event to PMC (Power Manage-

ment Controller)

—

Generates interrupts to ICU

—

Provides user-selectable trigger conditions

General-Purpose I/O (GPIO)

—

84/117 port pins in 128-pin/176-pin package, re-

spectively.

—

I/O pins individually conﬁgured as input or output

—

Conﬁgurable internal pull-up resistors

—

Special ports for internal keyboard matrix scanning

❏

16 open-collector outputs

❏

Pulse Width Modulation (PWM) Module

—

Eight outputs

—

8-bit duty cycle resolution

—

Common input clock prescaler

Timer and WATCHDOG (TWM)

—

16-bit periodic interrupt timer with 30

µs

resolution

and 5-bit prescaler for system tick and periodic

wake-up tasks

—

8-bit WATCHDOG timer

Analog to Digital Converter (ADC)

—

Fourteen channels, with 10-bit resolution

—

Sigma-delta technology for high noise rejection

—

Three voltage measurements and one temperature

measurement every 100 ms

—

Internal voltage reference

Hardware Monitoring

—

Controlled by embedded controller

—

System Voltage Measurement

❏

Up to eight external measurement points

❏

Eight Schmitt inputs with internal pull-ups

Four internal measurement points

Smart power failure detection

—

Input for system On/Off switch

—

27 external wake-up events

—

Low-cost external GPIO expansion through the

BIU I/O Expansion protocol

—

Diode-Based Temperature Measurement

❏

Software-controlled fault detection

❏

Hardware-monitored over-temperature detection

PS/2 Interface

—

Supports four external ports: Keyboard, mouse and

two additional pointing devices

—

Supports byte-level handling via hardware accelera-

tor

Two ACCESS.bus (ACB) Interface modules. Each is:

—

Intel

and Philips

compatible

ACCESS.bus master and slave

Up to three simultaneous slave addresses detected

Supports polling and interrupt controlled operation

Generates a wake-up signal on detection of a Start

Condition while in Idle mode

—

Optional internal pull-up on SDA and SCL pins

SMBus

—

Production time calibration using ﬂash parameters

Digital to Analog Converter (DAC)

—

Four channels, 8-bit resolution

—

µs

conversion time for 50 pF load

—

Full output range from AGND to AVCC

Analog Comparators Monitor (ACM)

—

Eight comparator inputs on KBD scan inputs

—

6-bit input measurement resolution

—

Scan and Threshold modes

—

Supports low-current system wake-up

Development Support Features

—

Interface to debugger via JTAG pins

❏

ISE/ADB mode

❏

Two 16-bit Multi Function Timer (MFT16) modules.

Each module:

—

Contains two 16-bit timers

—

Supports Pulse Width Modulation (PWM), Capture

and Counter

Universal Synchronous/ Asynchronous Receiver-trans-

mitter (USART)

—

A full-duplex USART channel

—

Programmable baud rate

—

Data transfer via interrupt or polling

—

Synchronous mode with either internal or external

clock

—

7-, 8- or 9-bit protocols.

On-board Debug mode

—

Flash programing via JTAG

CR16B Access to Host Controlled Functions

—

Enabled when host inactive

Host Controlled Functions Features

Supports

Microsoft

Advanced Power Management

(APM) Speciﬁcations Revision 1.2,

February 1996

—

Generates the System Management Interrupt (SMI)

PC1 and ACPI Compliant

—

PnP Conﬁguration Register structure

—

Flexible resource allocation for all logical devices

❏

Relocatable base address

Revision 1.06

www.national.com

PC87591E/S/L

Features

❏

(Continued)

15 IRQ routing options

Legacy free support

Real-Time Clock (RTC)

—

DS1287 and MC146818 compatible

—

242-byte battery backed-up CMOS RAM

—

Calendar including century and automatic leap-year

adjustment (Y2K compliant)

—

Optional adjustment for daylight saving time

—

BCD or binary format for timekeeping

—

Three individually maskable interrupt event ﬂags:

periodic rates from 122

µs

to 500 ms; time-of-day

alarm, once-per-second to once-per-day

—

Double-buffer time registers

—

Alarm wake-up

Mobile System Wake-Up Control (MSWC)

—

Wake-up on detection of RI1, RI2, RING activity

❏

External modem ring on serial port

❏

Clocks

—

Single 32.768 KHz crystal oscillator

—

LPC clock, up to 33 MHz

—

On-chip high frequency clock generator

❏

CPU clock 4-20 MHz

❏

Software-controlled frequency generation

Multiplier source 32 KHz input

—

32 KHz clock out

—

CR16B clock out

Power Supply

—

3.3V supply operation

—

5V tolerance and back-drive protection on all pins

(except LPC bus pins and keyboard scan inputs)

—

Separate supply for Host I/F (V

) and Embedded

Controller functions (V

)

—

Backup battery input for RTC, and wake-up conﬁgu-

ration.

—

Reduced power consumption capability

—

Four power modes, switched by software or hard-

ware

❏

Active mode current (TBD mA)

❏

Ring pulse or pulse train on RING input signal

Software-controlled off events

—

Optional routing of power-up request on IRQ and/or

SMI lines

Clocking, Supply and Package Information

Active mode executing WAIT

Idle (15

µA)

Power off for RTC only (0.9

µA

typical) from

backup battery

❏

Strap Input Controlled Operating Modes

—

Turn on shared BIOS

—

TRI-STATE

—

Development

—

On-board development

—

Programing environment

—

Automatic wake-up on system events

Package Options

—

128-pin LQFP and CSP packages

—

176-pin LQFP and CSP packages for more GPIO

pins, Expansion Memory use and development sys-

tems

www.national.com

Revision1.06

PC87591E/S/L

Revision Record

Revision Date

April 11, 00

December 25, 00

May 1, 01

May 8, 01

July 19, 01

October 28, 01

March 26, 02

Status

0.13

1.0

1.02

1.03

1.04

1.05

1.06

Comments

External version of Architectural Speciﬁcation

Preliminary

Revision 1.06

www.national.com

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PC87591S-SLB128 Related Products

	PC87591S-SLB128	PC87591S-SLB176	PC87591E-SLB128	PC87591E-SLB176	PC87591L-SLB176
Description	RISC Microcontroller, 16-Bit, FLASH, 20MHz, CMOS, PBGA128, CSP-128	RISC Microcontroller, 16-Bit, FLASH, 20MHz, CMOS, PBGA176, CSP-176	RISC Microcontroller, 16-Bit, FLASH, 20MHz, CMOS, PBGA128, CSP-128	RISC Microcontroller, 16-Bit, FLASH, 20MHz, CMOS, PBGA176, CSP-176	RISC Microcontroller, 16-Bit, FLASH, 20MHz, CMOS, PBGA176, CSP-176
Maker	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation
Parts packaging code	BGA	BGA	BGA	BGA	BGA
package instruction	TFLGA,	TFLGA,	TFLGA,	TFLGA,	TFLGA,
Contacts	128	176	128	176	176
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
ECCN code	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2
Has ADC	YES	YES	YES	YES	YES
Address bus width	8	20	8	20	20
bit size	16	16	16	16	16
maximum clock frequency	33 MHz	33 MHz	33 MHz	33 MHz	33 MHz
DAC channel	YES	YES	YES	YES	YES
DMA channel	YES	YES	YES	YES	YES
External data bus width	8	16	8	16	16
JESD-30 code	S-PBGA-B128	S-PBGA-B176	S-PBGA-B128	S-PBGA-B176	S-PBGA-B176
length	10 mm	13 mm	10 mm	13 mm	13 mm
Number of I/O lines	62	93	62	93	93
Number of terminals	128	176	128	176	176
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C
PWM channel	YES	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFLGA	TFLGA	TFLGA	TFLGA	TFLGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
ROM programmability	FLASH	FLASH	FLASH	FLASH	FLASH
Maximum seat height	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm
speed	20 MHz	20 MHz	20 MHz	20 MHz	20 MHz
Maximum supply voltage	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BUTT	BUTT	BUTT	BUTT	BUTT
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	10 mm	13 mm	10 mm	13 mm	13 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC

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