MT54V1MH18AF-7.5 datasheet, PDF

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MT54V1MH18AF-7.5: DescriptionQDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size375KB，25 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT54V1MH18AF-7.5 Overview

QDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

MT54V1MH18AF-7.5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	BGA
package instruction	13 X 15 MM, 1 MM PITCH, FBGA-165
Contacts	165
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	3 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	QDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	1.5,2.5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.125 A
Minimum standby current	2.4 V
Maximum slew rate	0.31 mA
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb2 SRAM

18Mb QDR SRAM

2-WORD BURST

Features

• Separate independent read and write data ports

with concurrent transactions

• 100 percent bus utilization DDR READ and WRITE

operation

• High frequency operation with future migration to

higher clock frequencies

• Fast clock to valid data times

• Full data coherency, providing most current data

• Two-tick burst counter for low DDR transaction size

• Double data rate operation on read and write ports

• Two input clocks (K and K#) for precise DDR timing

at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching—clock and data delivered

together to receiving device

• Optional-use echo clocks (CQ and CQ#) for flexible

receive data synchronization

• Single address bus

• Simple control logic for easy depth expansion

• Internally self-timed, registered writes

• 2.5V core and 1.5 to 1.8V (±0.1V) HSTL I/O

• Clock-stop capability

• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

package

• User-programmable impedance output

• JTAG boundary scan

™

MT54V1MH18A

MT54V512H36A

Figure 1: 165-Ball FBGA

Table 1:

Valid Part Numbers

DESCRIPTION

1 Meg x 18, QDRb2 FBGA

512K x 36, QDRb2 FBGA

PART NUMBER

MT54V1MH18AF-xx

MT54V512H36AF-xx

General Description

Options

• Clock Cycle Timing

6ns (167 MHz)

7.5ns (133 MHz)

10ns (100 MHz)

• Configurations

1 Meg x 18

512K x 36

• Package

165-ball, 13mm x 15mm FBGA

• Operating Temperature Range

Commercial (0°C

+70°C)

NOTE:

Marking

-6

-7.5

-10

MT54V1MH18A

MT54V512H36A

None

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

The Micron

QDR™ (Quad Data Rate™) synchro-

nous, pipelined burst SRAM employs high-speed, low-

power CMOS designs using an advanced 6T CMOS

process.

The QDR architecture consists of two separate DDR

(double data rate) ports to access the memory array.

The read port has dedicated data outputs to support

READ operations. The write port has dedicated data

inputs to support WRITE operations. This architecture

eliminates the need for high-speed bus turnaround.

Access to each port is accomplished using a common

address bus. Addresses for reads and writes are latched

on rising edges of the K and K# input clocks, respec-

tively. Each address location is associated with two

words that burst sequentially into or out of the device.

Since data can be transferred into and out of the device

on every rising edge of both clocks (K and K# and C

and C#), memory bandwidth is maximized and system

design is simplified by eliminating bus turnarounds.

18Mb: 2.5V V

, HSTL, QDRb2 SRAM

MT54V1MH18A_16_F.fm – Rev. F, Pub. 3/03

MT54V1MH18AF-7.5 Related Products

	MT54V1MH18AF-7.5	MT54V512H36AF-6	MT54V512H36AF-10	MT54V512H36AF-7.5
Description	QDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	QDR SRAM, 512KX36, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	QDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	QDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	Micron Technology	Micron Technology	Micron Technology	Micron Technology
Parts packaging code	BGA	BGA	BGA	BGA
package instruction	13 X 15 MM, 1 MM PITCH, FBGA-165	13 X 15 MM, 1 MM PITCH, FBGA-165	13 X 15 MM, 1 MM PITCH, FBGA-165	13 X 15 MM, 1 MM PITCH, FBGA-165
Contacts	165	165	165	165
Reach Compliance Code	not_compliant	unknown	not_compliant	not_compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	3 ns	2.5 ns	3 ns	3 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz	166 MHz	125 MHz	133 MHz
I/O type	SEPARATE	SEPARATE	SEPARATE	SEPARATE
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
JESD-609 code	e0	e0	e0	e0
length	15 mm	15 mm	15 mm	15 mm
memory density	18874368 bit	18874368 bit	18874368 bit	18874368 bit
Memory IC Type	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM
memory width	18	36	36	36
Number of functions	1	1	1	1
Number of terminals	165	165	165	165
word count	1048576 words	524288 words	524288 words	524288 words
character code	1000000	512000	512000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	1MX18	512KX36	512KX36	512KX36
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TBGA	TBGA	TBGA	TBGA
Encapsulate equivalent code	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	1.5,2.5 V	1.5,2.5 V	1.5,2.5 V	1.5,2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum standby current	0.125 A	0.16 A	0.12 A	0.135 A
Minimum standby current	2.4 V	2.4 V	2.4 V	2.4 V
Maximum slew rate	0.31 mA	0.5 mA	0.3 mA	0.4 mA
Maximum supply voltage (Vsup)	2.6 V	2.6 V	2.6 V	2.6 V
Minimum supply voltage (Vsup)	2.4 V	2.4 V	2.4 V	2.4 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	13 mm	13 mm	13 mm	13 mm

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