MC74VHC1G126
Noninverting 3-State Buffer
The MC74VHC1G126 is an advanced high speed CMOS
noninverting 3−state buffer fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including a buffered
3−state output which provides high noise immunity and stable output.
The MC74VHC1G126 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G126 to be used to interface 5 V circuits to 3 V
circuits.
Features
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MARKING
DIAGRAMS
5
1
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
5
W2 M
G
G
M
•
•
•
•
•
•
•
High Speed: t
PD
= 3.5 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 1
mA
(Max) at T
A
= 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 58; Equivalent Gates = 15
These Devices are Pb−Free and are RoHS Compliant
1
5
5
1
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
1
W2 M
G
G
OE
1
5
V
CC
W2 = Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
IN A
2
PIN ASSIGNMENT
GND
3
4
OUT Y
1
2
3
4
5
OE
IN A
OE
IN A
GND
OUT Y
V
CC
Figure 1. Pinout
(Top View)
EN
OUT Y
A Input
FUNCTION TABLE
OE Input
H
H
L
Y Output
L
H
Z
L
H
X
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
May, 2011
−
Rev. 15
1
Publication Order Number:
MC74VHC1G126/D
MC74VHC1G126
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
q
JA
T
L
T
J
T
stg
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, V
CC
and GND
Power dissipation in still air
Thermal resistance
Lead temperature, 1 mm from case for 10 secs
Junction temperature under bias
Storage temperature
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Above V
CC
and Below GND at 125°C (Note 4)
SC−88A, TSOP−5
SC−88A, TSOP−5
V
OUT
< GND; V
OUT
> V
CC
V
CC
= 0
High or Low State
Characteristics
Value
−0.5
to +7.0
−0.5
to +7.0
−0.5
to 7.0
−0.5
to V
CC
+ 0.5
−20
+20
+25
+50
200
333
260
+150
−65
to +150
> 2000
> 200
N/A
±500
Unit
V
V
V
mA
mA
mA
mA
mW
°C/W
°C
°C
°C
V
I
Latchup
Latchup Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature Range
Input Rise and Fall Time
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
Characteristics
Min
2.0
0.0
0.0
−55
0
0
Max
5.5
5.5
V
CC
+125
100
20
Unit
V
V
V
°C
ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
NORMALIZED FAILURE RATE
Junction
Temperature
°C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 130
°
C
TJ = 100
°
C
TJ = 120
°
C
TJ = 110
°
C
TJ = 80
°
C
100
TIME, YEARS
TJ = 90
°
C
1
1
10
1000
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1G126
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
Parameter
Minimum High−Level
Input Voltage
Test Conditions
V
CC
(V)
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
V
IN
= V
IH
or V
IL
I
OH
=
−50
mA
V
IN
= V
IH
or V
IL
I
OH
=
−4
mA
I
OH
=
−8
mA
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50
mA
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
I
OZ
I
IN
I
CC
Maximum 3−State
Leakage Current
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
5.5
0 to
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.2
5
±0.1
1.0
2.0
3.0
4.5
T
A
= 25°C
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
±2.5
±1.0
20
Typ
Max
T
A
≤
85°C
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
1.9
2.9
4.4
2.34
3.66
0.1
0.1
0.1
0.52
0.52
±2.5
±1.0
40
Max
−55
≤
T
A
≤
125°C
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
Max
Unit
V
V
IL
Maximum Low−Level
Input Voltage
V
V
OH
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
V
V
V
mA
mA
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
ÎÎ Î Î ÎÎ Î Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎ Î Î ÎÎ Î Î Î
Î Î Î ÎÎ Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
Î Î Î ÎÎ Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î ÎÎ Î Î Î
Î
Î
Î Î Î ÎÎ Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î Î Î ÎÎ Î Î Î
Î Î ÎÎ Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
Î Î Î ÎÎ Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î Î Î ÎÎ Î Î Î
Î Î ÎÎ Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎ Î Î ÎÎ Î Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î ÎÎ Î Î Î
Î
Î
Î Î Î ÎÎ Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î Î Î ÎÎ Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î ÎÎ Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
Î Î Î ÎÎ Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS
C
load
= 50 pF, Input t
r
= t
f
= 3.0 ns
Symbol
t
PLH
,
t
PHL
Parameter
Test Conditions
Min
T
A
= 25°C
Typ
4.5
6.4
3.5
4.5
4.5
6.4
3.5
4.5
6.5
8.0
4.8
7.0
4.0
6.0
T
A
≤
85°C
−55
≤
T
A
≤
125°C
Min
Max
12.0
16.0
Max
8.0
11.5
5.5
7.5
Min
Max
Unit
ns
Maximum Propagation
Delay, Input A to Y
(Figures 3. and 5.)
V
CC
= 3.3
±
0.3 V
V
CC
= 5.0
±
0.5 V
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
9.5
13.0
6.5
8.5
8.5
10.5
t
PZL
,
t
PZH
Maximum Output Enable
Time, Input OE to Y
(Figures 4. and 5.)
V
CC
= 3.3
±
0.3 V
R
L
= 1000
W
V
CC
= 5.0
±
0.5 V
R
L
= 1000
W
V
CC
= 3.3
±
0.3 V
R
L
= 1000
W
V
CC
= 5.0
±
0.5 V
R
L
= 1000
W
8.0
11.5
5.1
7.1
9.5
13.0
6.0
8.0
11.5
15.0
ns
8.5
10.5
t
PLZ
,
t
PHZ
Maximum Output Disable
Time, Input OE to Y
(Figures 4. and 5.)
9.7
13.2
6.8
8.8
10
11.5
15.0
14.5
18.0
10.0
12.0
10
ns
8.0
10.0
10
C
IN
Maximum Input
Capacitance
pF
pF
C
OUT
Maximum 3−State Output
Capacitance (Output in
High Impedance State)
Typical @ 25°C, V
CC
= 5.0 V
8.0
C
PD
Power Dissipation Capacitance (Note 5)
pF
5. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the no−load dynamic
power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
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3
MC74VHC1G126
SWITCHING WAVEFORMS
V
CC
50%
GND
V
CC
50%
A
t
PLH
50% V
CC
Y
t
PHL
Y
GND
Y
t
PZL
50% V
CC
t
PZH
50% V
CC
t
PHZ
t
PLZ
HIGH
IMPEDANCE
V
OL
+ 0.3V
V
OH
- 0.3V
HIGH
IMPEDANCE
OE
Figure 4. Switching Waveforms
Figure 5.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH.
C
L
*
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
ORDERING INFORMATION
Device
M74VHC1G126DFT1G
M74VHC1G126DFT2G
M74VHC1G126DTT1G
Package
SC−88A/SOT−353/SC−70
(Pb−Free)
SC−88A/SOT−353/SC−70
(Pb−Free)
TSOP−5/SOT−23/SC−59
(Pb−Free)
3000 Units / Tape & Reel
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1G126
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
A
G
5
4
S
1
2
3
−B−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
---
0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
---
0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
D
5 PL
0.2 (0.008)
M
B
M
N
J
C
DIM
A
B
C
D
G
H
J
K
N
S
H
K
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