Order this document by AM26LS30/D
AM26LS30
Dual Differential (EIA-422-A)/
Quad Single-Ended
(EIA-423-A) Line Drivers
The AM26LS30 is a low power Schottky set of line drivers which can be
configured as two differential drivers which comply with EIA–422–A
standards, or as four single–ended drivers which comply with EIA–423–A
standards. A mode select pin and appropriate choice of power supplies
determine the mode. Each driver can source and sink currents in excess of
50 mA.
In the differential mode (EIA–422–A), the drivers can be used up to
10 Mbaud. A disable pin for each driver permits setting the outputs into a
high impedance mode within a
±10
V common mode range.
In the single–ended mode (EIA–423–A), each driver has a slew rate
control pin which permits setting the slew rate of the output signal so as to
comply with EIA–423–A and FCC requirements and to reduce crosstalk.
When operated from symmetrical supplies (±5.0 V), the outputs exhibit zero
imbalance.
The AM26LS30 is available in a 16–pin plastic DIP and surface mount
package. Operating temperature range is –40° to +85°C.
•
Operates as Two Differential EIA–422–A Drivers, or Four Single–Ended
EIA–423–A Drivers
•
High Impedance Outputs in Differential Mode
DUAL DIFFERENTIAL/
QUAD SINGLE–ENDED
LINE DRIVERS
SEMICONDUCTOR
TECHNICAL DATA
PC SUFFIX
PLASTIC PACKAGE
CASE 648
FN SUFFIX
PLASTIC PACKAGE
CASE 775
D SUFFIX
PLASTIC PACKAGE
CASE 751B
(SO–16)
•
•
•
•
•
•
Short Circuit Current Limit In Both Source and Sink Modes
±
10 V Common Mode Range on High Impedance Outputs
±
15 V Range on Inputs
Low Current PNP Inputs Compatible with TTL, CMOS, and MOS
Outputs
Individual Output Slew Rate Control in Single–Ended Mode
Replacement for the AMD AM25LS30 and National Semiconductor
DS3691
PIN CONNECTIONS
VCC
Input A
Input B/
Enable AB
Mode
Gnd
Input C/
Enable CD
Input D
VEE
1
2
3
4
5
6
7
8
(Top View)
Input A
SR–A
Out A
Out B
SR–B
NC
SR–C
Out C
17
16
15
9
In D
14
10 11 12 13
VEE
NC
SR–D
Out D
VCC
NC
16 SR–A
15 Output A
14 Output B
13 SR–B
12 SR–C
11 Output C
10 Output D
9 SR–D
Representative Block Diagrams
3
In B/En AB
4
5
6
7
8
2
1
20 19
18
Single–Ended Mode
EIA–423–A
SR–A
Input A
Out A
SR–B
Input B
Out B
SR–C
Input C
Out C
SR–D
Input D
Out D
Differential Mode
EIA–422–A
Enable AB
Input A
Out A
Out B
Out C
Out D
Mode
NC
Gnd
In C/En CD
Input D
ORDERING INFORMATION
Device
Operating
Temperature Range
TA = – 40° to +85°C
Package
Plastic DIP
SO–16
PLCC–20
Rev 0
Enable CD
VCC – 1
VEE – 8
Gnd – 5
Mode – 4
AM26LS30PC
MC26LS30D
AM26LS30FN
©
Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
1
AM26LS30
MAXIMUM OPERATING CONDITIONS
(Pin numbers refer to DIP and SO–16
packages only.)
Rating
Power Supply Voltage
Input Voltage (All Inputs)
Applied Output Voltage when in High Impedance Mode
(VCC = 5.0 V, Pin 4 = Logic 0, Pins 3, 6 = Logic 1)
Output Voltage with VCC, VEE = 0 V
Output Current
Junction Temperature
Symbol
VCC
VEE
Vin
Vza
Vzb
IO
TJ
Value
–0.5, +7.0
–7.0, +0.5
–0.5, +20
±15
±15
Self limiting
–65, +150
–
°C
Unit
Vdc
Vdc
Vdc
Devices should not be operated at these limits. The “Recommended Operating Conditions” table provides
conditions for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage (Differential Mode)
Power Supply Voltage (Single–Ended Mode)
Input Voltage (All Inputs)
Applied Output Voltage (when in High Impedance Mode)
Applied Output Voltage, VCC = 0
Output Current
Operating Ambient Temperature (See text)
All limits are not necessarily functional concurrently.
Symbol
VCC
VEE
VCC
VEE
Vin
Vza
Vzb
IO
TA
Min
+4.75
–0.5
+4.75
–5.25
0
–10
–10
–65
–40
Typ
5.0
0
+5.0
–5.0
–
–
–
–
–
Max
+5.25
+0.3
+5.25
–4.75
+15
+10
+10
+65
+85
Unit
Vdc
Vdc
mA
°C
ELECTRICAL CHARACTERISTICS
(EIA–422–A differential mode, Pin 4
Characteristic
Output Voltage (see Figure 1)
Differential, RL =
∞,
VCC = 5.25 V
Differential, RL = 100
Ω,
VCC = 4.75 V
Change in Differential Voltage, RL = 100
Ω
(Note 4)
Offset Voltage, RL = 100
Ω
Change in Offset Voltage*, RL = 100
Ω
Output Current (each output)
Power Off Leakage, VCC = 0, –10 V
VO
+10 V
High Impedance Mode, VCC = 5.25 V, –10 V
VO
+10 V
Short Circuit Current (Note 2)
High Output Shorted to Pin 5 (TA = 25°C)
High Output Shorted to Pin 5 (–40°C
TA +85°C)
Low Output Shorted to +6.0 V (TA = 25°C)
Low Output Shorted to +6.0 V (–40°C
TA
+85°C)
Inputs
Low Level Voltage
High Level Voltage
Current @ Vin = 2.4 V
Current @ Vin = 15 V
Current @ Vin = 0.4 V
Current, 0
Vin
15 V, VCC = 0
Clamp Voltage (Iin = –12 mA)
VEE = Gnd, unless otherwise noted. Pin numbers refer to DIP and SO–16 packages only.)
Symbol
VOD1
VOD2
∆V
OD2
VOS
∆V
OS
IOLK
IOZ
ISC–
ISC–
ISC+
ISC+
VIL
VIH
IIH
IIHH
IIL
IIX
VIK
ICC
p
0.8 V, –40°C
t
TA
t
85°C, 4.75 V
p
VCC
p
5.25 V,
Min
–
2.0
–
–
–
–100
–100
–150
–150
60
50
–
2.0
–
–
–200
–
–1.5
–
Typ
4.2
2.6
10
2.5
10
0
0
–95
–
75
–
–
–
0
0
–8.0
0
–
16
Max
6.0
–
400
3.0
400
+100
+100
–60
–50
150
150
0.8
–
40
100
–
–
–
30
Unit
Vdc
Vdc
mVdc
Vdc
mVdc
µA
p p
p p
t t
t t
mA
Vdc
Vdc
µA
p p
p
Vdc
mA
Power Supply Current (VCC = +5.25 V, Outputs Open)
(0
Enable
VCC)
p
NOTES:
1. All voltages measured with respect to Pin 5.
2. Only one output shorted at a time, for not more than 1 second.
3. Typical values established at +25°C, VCC = +5.0 V, VEE = –5.0 V.
4. Vin switched from 0.8 to 2.0 V.
5. Imbalance is the difference between
VO2
with Vin
0.8 V and
VO2
with Vin
t
u
2.0 V.
MOTOROLA ANALOG IC DEVICE DATA
2
AM26LS30
TIMING CHARACTERISTICS
(EIA–422–A differential mode, Pin 4
unless otherwise noted.)
Characteristic
Differential Output Rise Time (Figure 3)
Differential Output Fall Time (Figure 3)
Propagation Delay Time – Input to Differential Output
Input Low to High (Figure 3)
Input High to Low (Figure 3)
Skew Timing (Figure 3)
t
PDH to tPDL
for Each Driver
Max to Min tPDH Within a Package
Max to Min tPDL Within a Package
Enable Timing (Figure 4)
Enable to Active High Differential Output
Enable to Active Low Differential Output
Enable to 3–State Output From Active High
Enable to 3–State Output From Active Low
p
0.8 V, TA = 25°C, VCC = 5.0 V, VEE = Gnd, (Notes 1 and 3)
Symbol
tr
tf
tPDH
tPDL
tSK1
tSK2
tSK3
tPZH
tPZL
tPHZ
tPLZ
Min
–
–
–
–
–
–
–
–
–
–
–
Typ
70
70
90
90
9.0
2.0
2.0
150
190
80
110
Max
200
200
200
200
ns
–
–
–
ns
300
350
350
300
Unit
ns
ns
ns
ELECTRICAL CHARACTERISTICS
(EIA–423–A single–ended mode, Pin 4
|VEE
p
5.25 V,
(Notes 1 and 3) unless otherwise noted).
Characteristic
q
2.0 V, –40°C
t
TA
t
85°C, 4.75 V
p
VCC
,
Symbol
VO1
VO2
∆V
O2
ISLEW
Min
4.0
3.6
–
–
–100
60
50
–150
–150
–
2.0
–
–
–200
–
–1.5
–
–22
Typ
4.2
3.95
0.05
±120
0
80
–
–95
–
–
–
0
0
– 8.0
0
–
17
– 8.0
Max
6.0
6.0
0.4
–
+100
150
150
–60
–50
0.8
–
40
100
–
–
–
30
–
µA
µA
mA
Unit
Vdc
Output Voltage (VCC =
VEE
= 4.75 V)
Single–Ended Voltage, RL =
∞
(Figure 2)
Single–Ended Voltage, RL = 450
Ω,
(Figure 2)
Voltage Imbalance (Note 5), RL = 450
Ω
Slew Control Current (Pins 16, 13, 12, 9)
Output Current (Each Output)
Power Off Leakage, VCC = VEE = 0, –6.0 V
VO
+6.0 V
Short Circuit Current (Output Short to Ground, Note 2)
0.8 V (TA = 25°C)
Vin
Vin
0.8 V (–40°C
TA
+85°C)
Vin
2.0 V (TA = 25°C)
Vin
2.0 V (–40°C
TA
+85°C)
Inputs
Low Level Voltage
High Level Voltage
Current @ Vin = 2.4 V
Current @ Vin = 15 V
Current @ Vin = 0.4 V
Current, 0
Vin
15 V, VCC = 0
Clamp Voltage (Iin = –12 mA)
p
p
w
w
p p
IOLK
ISC+
ISC+
ISC–
ISC–
VIL
VIH
IIH
IIHH
IIL
IIX
VIK
ICC
IEE
t t
t t
Vdc
Vdc
µA
p p
Vdc
mA
Power Supply Current (Outputs Open)
VCC = +5.25 V, VEE = –5.25 V, Vin = 0.4 V
TIMING CHARACTERISTICS
(EIA–423–A single–ended mode, Pin 4
unless otherwise noted.)
Characteristic
Output Timing (Figure 5)
Output Rise Time, CC = 0
Output Fall Time, CC = 0
Output Rise Time, CC = 50 pF
Output Fall Time, CC = 50 pF
Rise Time Coefficient (Figure 16)
Propagation Delay Time, Input to Single Ended Output (Figure 5)
Input Low to High, CC = 0
Input High to Low, CC = 0
Skew Timing, CC = 0 (Figure 5)
t
PDH to tPDL
for Each Driver
Max to Min tPDH Within a Package
Max to Min tPDL Within a Package
q
2.0 V, TA = 25°C, VCC = 5.0 V, VEE = –5.0 V, (Notes 1 and 3)
Symbol
tr
tf
tr
tf
Crt
tPDH
tPDL
tSK4
tSK5
tSK6
Min
–
–
–
–
–
–
–
–
–
–
Typ
65
65
3.0
3.0
0.06
100
100
15
2.0
5.0
Max
300
300
–
–
–
300
300
ns
–
–
–
Unit
ns
µs
µs/pF
ns
MOTOROLA ANALOG IC DEVICE DATA
3
AM26LS30
Table 1
Inputs
Operation
Differential
(EIA–422–A)
(EIA 422 A)
VCC
+5.0
VEE
Gnd
Mode
0
0
0
0
0
0
1
1
1
1
1
X
A
0
1
X
1
0
1
0
1
0
0
0
X
B
0
0
1
0
0
0
0
0
1
0
0
X
C
0
0
0
0
0
1
0
0
0
1
0
X
D
0
1
1
0
1
X
0
0
0
0
1
X
A
0
1
Z
1
0
1
0
1
0
0
0
Z
Outputs
B
1
0
Z
0
1
0
0
0
1
0
0
Z
C
1
0
0
1
0
Z
0
0
0
1
0
Z
D
0
1
1
0
1
Z
0
0
0
0
1
Z
Single–Ended
g
(EIA–423–A)
(EIA 423 A)
+5.0
–5.0
X
X = Don’t Care
Z = High Impedance (Off)
0
X
Figure 1. Differential Output Test
VCC
RL/2
Vin
(0.8 or 2.0 V)
Mode = 0
VOD2
RL/2
VOS
Figure 2. Single–Ended Output Test
VCC
Vin
(0.8 or 2.0 V)
RL
Mode = 1
VEE
CL
VO
Figure 3. Differential Mode Rise/Fall Time and Data Propagation Delay
VCC
Vin
Vin
100
500 pF
VOD
+3.0 V
1.5 V
0V
tPDL
90%
50%
10%
tr
tf
1.5 V
tPDH
S.G.
90%
50%
Vout 10%
NOTES:
1. S.G. set to: f
1.0 MHz; duty cycle = 50%; tr, tf,
10 ns.
2. tSK1 =
tPDH–tPDL
for each driver.
3. tSK2 computed by subtracting the shortest tPDH from the longest tPDH of the 2 drivers within a package.
4. tSK3 computed by subtracting the shortest tPDL from the longest tPDL of the 2 drivers within a package.
p
p
4
MOTOROLA ANALOG IC DEVICE DATA
AM26LS30
Figure 4. Differential Mode Enable Timing
VCC
0 or 3.0 V
Vin
500 pF
En
450
Ω
RL V
SS
+3.0 V
1.5 V
tPHZ
(Vin = Hi)
Output
Current
tPLZ
(Vin = Lo)
0.1 VSS/RL
VSS/RL
tPZL
0.1 VSS/RL
tPZH
VSS/RL
0.5 VSS/RL
1.5 V
0V
Vin
S.G.
0.5 VSS/RL
NOTES:
1. S.G. set to: f
1.0 MHz; duty cycle = 50%; tr, tf,
10 ns.
2. Above tests conducted by monitoring output current levels.
p
p
Figure 5. Single–Ended Mode Rise/Fall Time and Data Propagation Delay
VCC
Vin
CC
450
VEE
S.G.
500 pF
Vin
1.5 V
tPDH
VO
Vout
+2.5 V
1.5 V
0V
tPDL
90%
50%
10%
tr
NOTES:
1. S.G. set to: f
100 kHz; duty cycle = 50%; tr, tf, 10 ns.
2. tSK4 =
tPDH–tPDL
for each driver.
3. tSK5 computed by subtracting the shortest tPDH from the longest tPDH of the 4 drivers within a package.
4. tSK6 computed by subtracting the shortest tPDL from the longest tPDL of the 4 drivers within a package.
90%
50%
10%
tf
p
p
MOTOROLA ANALOG IC DEVICE DATA
5
Embedded System
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