GS8662D37AGE-400I datasheet, PDF

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GS8662D37AGE-400I: DescriptionDDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; Categorystorage storage; File Size868KB，30 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8662D37AGE-400I Overview

DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8662D37AGE-400I Parametric

Parameter Name	Attribute value
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	SYNCHRONOUS BURST
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

GS8662D37AGE-400I Preview

GS8662D19/37AE-400/375/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, and 36Mb and

future 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaQuad-II+

Burst of 4 SRAM

400 MHz–300 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaQuad™ Family Overview

The GS8662D19/37AE are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662D19/37AE SigmaQuad SRAMs are just

one element in a family of low power, low voltage HSTL I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

Clocking and Addressing Schemes

The GS8662D19/37AE SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Separate I/O SigmaQuad-II+ B4 RAMs always

transfer data in four packets, A0 and A1 are internally set to 0

for the first read or write transfer, and automatically

incremented by 1 for the next transfers. Because the LSBs are

tied off internally, the address field of a SigmaQuad-II+ B4

RAM is always two address pins less than the advertised index

depth (e.g., the 4M x 18 has a 1024K addressable index).

-400

tKHKH

tKHQV

2.5ns

0.45 ns

Parameter Synopsis

-375

2.67 ns

0.45 ns

-333

3.3 ns

0.45 ns

-300

3.0 ns

0.45 ns

Rev: 1.00a 7/2008

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8662D19/37AE-400/375/333/300

2M x 36 SigmaQuad-II SRAM—Top View

Q27

D27

D28

Q29

Q30

D30

Doff

D31

Q32

Q33

D33

D34

Q35

TDO

MCL/SA

(288Mb)

Q18

Q28

D20

D29

Q21

D22

REF

Q31

D32

Q24

Q34

D26

D35

TCK

D18

D19

Q19

Q20

D21

Q22

DDQ

D23

Q23

D24

D25

Q25

Q26

DDQ

BW2

BW3

QVLD

BW1

BW0

DDQ

D17

D16

Q16

Q15

D14

Q13

DDQ

D12

Q12

D11

D10

Q10

MCL/SA

(144Mb)

Q17

D15

Q14

D13

REF

Q11

TMS

TDI

11 x 15 Bump BGA—15 x 17 mm

Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35

2. MCL = Must Connect Low

Rev: 1.00a 7/2008

2/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8662D19/37AE-400/375/333/300

4M x 18 SigmaQuad-II SRAM—Top View

Doff

TDO

MCL/SA

(144Mb)

D11

Q12

D13

REF

Q15

D17

TCK

D10

Q10

Q11

D12

Q13

DDQ

D14

Q14

D15

D16

Q16

Q17

DDQ

BW1

QVLD

BW0

DDQ

REF

TMS

TDI

11 x 15 Bump BGA—15 x 17 mm

Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.

2. MCL = Must Connect Low

Rev: 1.00a 7/2008

3/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8662D19/37AE-400/375/333/300

Pin Description Table

Symbol

BW0–BW3

TMS

TDI

TCK

TDO

REF

off

DDQ

QVLD

Description

Synchronous Address Inputs

No Connect

Synchronous Read

Synchronous Write

Synchronous Byte Writes

Input Clock

Test Mode Select

Test Data Input

Test Clock Input

Test Data Output

HSTL Input Reference Voltage

Output Impedance Matching Input

Synchronous Data Outputs

Synchronous Data Inputs

Disable DLL when low

Output Echo Clock

Power Supply

Isolated Output Buffer Supply

Power Supply: Ground

Q Valid Output

Type

Input

—

Input

Output

Input

Output

Input

Output

Supply

Output

Comments

—

Active Low

x9/x18/x36 only

Active High

Active Low

—

Active Low

—

1.8 V Nominal

1.5 or 1.8 V Nominal

—

Notes:

1. NC = Not Connected to die or any other pin

2. When ZQ pin is directly connected to V

DDQ

, output impedance is set to minimum value and it cannot be connected to ground or left

unconnected.

3. K, or K cannot be set to V

REF

voltage.

Rev: 1.00a 7/2008

4/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8662D19/37AE-400/375/333/300

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

Alternating Read-Write Operations

SigmaQuad-II+ SRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted and re-started.

- R and W high always deselects the RAM.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for

details.

SigmaQuad-II+ B4 SRAM DDR Read

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command.

Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.

SigmaQuad-II+ B4 SRAM DDR Write

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous

command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge

of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.

Rev: 1.00a 7/2008

5/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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